Sonos ono stack scaling

ABSTRACT

A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.15/988,981, filed on May 24, 2018, which is a continuation of U.S.application Ser. No. 15/051,279, filed on Feb. 23, 2016, now U.S. Pat.No. 9,997,641, issued on Jun. 12, 2018, which is a continuation of U.S.application Ser. No. 13/539,461, filed Jul. 1, 2012, now U.S. Pat. No.9,299,568, issued on Mar. 29, 2016, which is a continuation-in-part ofU.S. application Ser. No. 11/904,506, filed Sep. 26, 2007, now U.S. Pat.No. 8,614,124, issued on Dec. 24, 2013, which claims the benefit ofpriority under 35 U.S.C. 119(e) to U.S. Provisional Patent ApplicationSer. No. 60/940,384, filed May 25, 2007, all of which are incorporatedby reference herein in their entirety.

TECHNICAL FIELD

Embodiments of the present invention relate to the electronicsmanufacturing industry and more particularly to fabrication ofnonvolatile trapped-charge memory devices.

BACKGROUND

FIG. 1 is a partial cross-sectional view of an intermediate structurefor a semiconductor device 100 having asemiconductor-oxide-nitride-oxide-semiconductor (SONOS) gate stack 102including a conventional oxide-nitride-oxide (ONO) stack 104 formed overa surface 106 of a semiconductor substrate 108 according to aconventional method. The device 100 typically further includes one ormore diffusion regions 110, such as source and drain regions, aligned tothe gate stack and separated by a channel region 112. The SONOS gatestack 102 includes a poly-silicon (poly) gate layer 114 formed upon andin contact with the ONO stack 104. The poly gate 114 is separated orelectrically isolated from the substrate 108 by the ONO stack 104. TheONO stack 104 generally includes a silicon oxide tunneling layer 116, asilicon nitride charge trapping layer 118 which serves as a chargestoring or memory layer for the device 100, and a silicon oxide blockinglayer 120 overlying the charge trapping layer 118.

Such SONOS-type transistors are useful for non-volatile memory (NVM).The charge trapping layer stores charge to provide non-volatility. Toprogram (i.e. write to) the n-channel SONOS-type device, a positivevoltage is applied to the control gate (Vcg) while the source, body anddrain are grounded. An energy band diagram, trapped charge distributionand trap density distribution of a conventional n-channel SONOS devicehaving a channel 212, oxide tunneling layer 216, nitride memory layer218 and oxide blocking layer 220 during programming is depicted in FIG.2. As shown, the positive Vcg produces a field across the SONOS stackresulting in some negative charge at the conduction band energy level inthe buried channel of silicon substrate channel to undergoFowler-Nordheim tunneling (FNT) through the tunneling layer and into thecharge trapping layer. The electrons are stored in traps having mid gapenergy levels in the charge trapping nitride. As illustrated, the trapdensity distribution is substantially uniform throughout the chargetrapping layer. As further shown, under bias, the trapped chargedistribution is such that the majority of trapped charge is in theportion of the charge trapping layer (i.e. memory layer) proximate tothe blocking oxide. To erase then-channel SONOS device, a negativevoltage is applied to the control gate 314. An energy band diagramshowing the channel 312, oxide tunneling layer 316, nitride memory layer318 and oxide blocking layer 320 during erasing is depicted in FIG. 3.As shown, the negative Vcg produces a field across the SONOS stackattracting hole tunneling charge through the tunneling layer and intothe charge trapping layer.

SONOS-type devices are gaining in popularity for high density memoryapplications, such as embedded NVM. It is known in the industry thatuniform channel Fowler-Nordheim tunneling (FNT) and/or direct tunneling(DT) for program and erase result in improved reliability over othermethods. A combination of FNT and DT is referred to here and is referredto as modified Fowler-Nordheim tunneling (MFNT). Currently, conventionalSONOS operate in the 10 V range for MFNT. However, an advantage of SONOSover other NVM devices is voltage scalability. It has been theorized,with proper scaling, there exists potential in SONOS to achieve a memorytechnology operable in the 5 volt (V) range, rather than the 10 V rangeof conventional SONOS-type devices or 12 V-15 V range of conventionalflash technology. SONOS-type devices operable at low voltages(approaching 5 V) are advantageously compatible with low voltage CMOS.Alternatively, faster programming or erasing may be possible at aparticular voltage for a scaled device. However, successful scaling ofSONOS-type devices is non-trivial. For example, FIG. 4 depictsprogramming and erase times for a conventional SONOS device employing aconventional ONO stack comprised of a 10 nm thick silicon dioxideblocking layer, a 7 nm thick silicon nitride charge trapping layer, anda 3 nm thick silicon dioxide tunneling layer. As shown, theprogramming/erase time increases dramatically when Vcg is scaled down.Generally, program/erase times less than 1 millisecond (ms) aredesirable for embedded memory applications. However, such 1 msprogram/erase times may be achieved in the conventional SONOS stack onlywith a Vcg of +/−10 V. Conventional SONOS program/erase times extend to100 ms or more when Vcg is reduced to approximately +/−9 v.

Furthermore, reducing the programming voltage results in a reduction ofthe erase or program window (i.e. memory window). This is because theelectric field is across the ONO stack is reduced if the equivalentoxide thickness (EOT) of the entire ONO stack is not scaled down as thevoltage is reduced. Reducing the EOT of the stack is non-trivial becausereducing the tunneling layer thickness to allow the same initial eraselevel at a lower applied voltage (Vcg) can result in a detrimentalincrease in the erase and program decay rate Similarly, if the chargetrapping layer thickness is reduced, the charge centroid is placedcloser to the substrate, increasing charge loss to the substrate.Finally, when the blocking oxide thickness is scaled down, the electronreverse injection from the control gate is increased, causing damage tothe ONO stack and data retention loss. Reverse injection is manifestedas further shown in FIG. 4, where the FNT erase reaches “saturation.”This occurs when electrons are back streamed from the gate into thememory layer faster than they can be removed via hole transport acrossthe tunnel oxide. Accordingly, there remains a need to scale the ONOstack of a SONOS device in a manner capable of providing a deviceoperable at a lower program/erase voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention are illustrated by way of example,and not limitation, in the figures of the accompanying drawings inwhich:

FIG. 1 illustrates a cross sectional view of an intermediate structurefor a conventional SONOS device.

FIG. 2 depicts an energy band diagram, trapped charge distribution andtrap density distribution of a conventional SONOS device during program.

FIG. 3 depicts an energy band diagram of a conventional SONOS deviceduring erase.

FIG. 4 depicts programming and erase times for a conventional SONOSdevice employing a conventional ONO stack.

FIG. 5 illustrates a cross-sectional side view of a portion of a scalednonvolatile trapped-charge memory device having a scaled ONO structureincluding a nitridized oxide tunneling layer, a multi-layer oxynitridecharge trapping layer and a densified blocking layer according to anembodiment of the present invention.

FIG. 6 illustrates an approximate nitrogen concentration profile of thenitridized oxide tunneling layer in accordance with an embodiment of thepresent invention.

FIG. 7A illustrates a graph depicting simulation showing reduction inprogramming voltage attributable to a nitridized oxide tunneling layerin accordance with an embodiment of the present invention.

FIG. 7B illustrates a comparison of two concentration profiles ofhydrogen, nitrogen, oxygen, and silicon in a blocking layer, chargetrapping layer and tunneling layer of two different SONOS-type devices.

FIG. 8A depicts a retention mode energy band diagram of a scaledSONOS-type device in accordance with an embodiment of the presentinvention.

FIG. 8B depicts energy band diagram, trapped charge distribution andtrap density distribution of a scaled SONOS-type device in accordancewith an embodiment of the present invention during program.

FIG. 9 is a flow chart of a SONOS scaling method of fabricating a scaledONO structure including a nitridized oxide tunneling layer, amulti-layer charge trapping layer and a reoxidized blocking layeraccording to an embodiment of the present invention.

FIG. 10 is a flow chart of a SONOS scaling method of forming anitridized oxide tunneling layer.

FIGS. 11A and 11B illustrates a cross-sectional side view of a portionof a scaled nonvolatile trapped-charge memory device having a scaled ONOstructure including a nitridized oxide tunneling layer, a multi-layercharge trapping layer and a densified blocking layer according to anembodiment of the present invention.

FIG. 12 is a flow chart of a method of forming a scaled nonvolatiletrapped-charge memory device having a scaled ONO structure including anitridized oxide tunneling layer, a split multi-layer charge trappinglayer and a densified blocking layer according to an embodiment of thepresent invention.

FIG. 13A illustrates a non-planar multigate device including anitridized oxide tunneling layer, a split multi-layer charge trappinglayer and a densified blocking layer according to an embodiment of thepresent invention.

FIG. 13B illustrates a cross-sectional view of the non-planar multigatedevice of FIG. 13A.

FIGS. 14A and 14B illustrate a non-planar multigate device including anitridized oxide tunneling layer, a split multi-layer charge trappinglayer, a densified blocking layer, and a horizontal nanowire channelaccording to an embodiment of the present invention.

FIG. 14C illustrates a cross-sectional view of a vertical string ofnon-planar multigate devices of FIG. 14A.

FIGS. 15A and 15B illustrate a non-planar multigate device including anitridized oxide tunneling layer, a split multi-layer charge trappinglayer, a densified blocking layer, and a vertical nanowire channel.

FIG. 16A through 16F illustrate a gate first scheme for fabricating thenon-planar multigate device of FIG. 15A.

FIG. 17A through 17F illustrate a gate last scheme for fabricating thenon-planar multigate device of FIG. 15A.

DETAILED DESCRIPTION

Embodiments of scaling a nonvolatile trapped-charge memory device aredescribed herein with reference to figures. However, particularembodiments may be practiced without one or more of these specificdetails, or in combination with other known methods, materials, andapparatuses. In the following description, numerous specific details areset forth, such as specific materials, dimensions and processesparameters etc. to provide a thorough understanding of the presentinvention. In other instances, well-known semiconductor design andfabrication techniques have not been described in particular detail toavoid unnecessarily obscuring the present invention. Referencethroughout this specification to “an embodiment” means that a particularfeature, structure, material, or characteristic described in connectionwith the embodiment is included in at least one embodiment of theinvention. Thus, the appearances of the phrase “in an embodiment” invarious places throughout this specification are not necessarilyreferring to the same embodiment of the invention. Furthermore, theparticular features, structures, materials, or characteristics may becombined in any suitable manner in one or more embodiments.

Certain embodiments of the present invention include a scaled SONOS-typedevice. In particular embodiments of the present invention, thetunneling layer, charge trapping layer and blocking layer are modifiedto scale the SONOS-type device. In particular embodiments, the scaledSONOS device is operable at programming and erase voltages below +/−10V. In certain such embodiments, the scaled SONOS device is operated withan erase voltage between −5 V and −9V, and preferably between −5 V and−7 V, to provide an initial erase voltage threshold level (VTE) of −1 to−3 V and preferably −2 to −3 after a 1 ms-10 ms pulse when operated attemperature of between −40 to 95 degrees Celsius (° C.). In otherspecific embodiments, the SONOS-type device is operated with aprogramming voltage between 5 V and 9V, and preferably between 5 V and 7V, to provide an initial program voltage threshold level (VTP) of 1 V to3 V, preferably 2 V to 3 V, after a 1 ms to 10 ms, preferably 5 ms,programming pulse. These exemplary scaled SONOS devices providing an endof life (EOL) memory window of between 1 V and 2 V after 20 years at 85°C. and at least 10,000 write/erase cycles, preferably 100,000 cycles.

In certain embodiments, a conventional pure oxygen (oxide) tunnelinglayer is replaced with a nitridized oxide having a particular nitrogenconcentration profile to reduce the equivalent oxide thickness of thetunneling layer relative to the pure oxygen tunneling layer whileretaining low interface trap density. This enables reducing (scaling)the programming/erase voltages while providing an erase voltagethreshold level (VTPNTE) as good or better than a conventional,non-scaled device. In particular other embodiments, the conventionalcharge trapping layer of nitride is replaced with a multi-layeroxynitride film having at least a top and bottom layer of distinctstoichiometry. In one such embodiment, the multi-layer oxynitrideincludes a silicon-rich, oxygen-lean top layer to locate and confine thecentroid of charge away from the tunnel oxide layer, thereby locallyincreasing trap density within the charge trapping layer. In particularother embodiments, the conventional blocking layer of high temperatureoxide (HTO) is replaced with a reoxidized blocking layer to densify theblocking oxide and thereby reduce the memory decay rate with scaling.Such embodiments provide sufficient net charge for an adequate memorywindow while also reducing trap assisted tunneling to improve ormaintain programming and erase threshold voltages (VTPNTE) when theSONOS device is operated at a reduced program/erase voltage.

The terms “over,” “under,” “between,” and “on” as used herein refer to arelative position of one layer with respect to other layers. As such,for example, one layer deposited or disposed over or under another layermay be directly in contact with the other layer or may have one or moreintervening layers. Moreover, one layer deposited or disposed betweenlayers may be directly in contact with the layers or may have one ormore intervening layers. In contrast, a first layer “on” a second layeris in contact with that second layer. Additionally, the relativeposition of one layer with respect to other layers is provided assumingoperations deposit, modify and remove films relative to a startingsubstrate without consideration of the absolute orientation of thesubstrate.

In accordance with one embodiment of the present invention, thenonvolatile trapped-charge memory device is a SONOS-type device whereina charge-trapping layer is an insulator layer, such as a nitride. Inanother embodiment, the nonvolatile trapped-charge memory device is aFlash-type device wherein the charge-trapping layer is a conductor layeror a semiconductor layer, such as poly-silicon. Nonvolatiletrapped-charge memory devices employing the nitridized oxide tunnelinglayer may enable a lower programming or erase voltage while providing anerase voltage threshold level (VTPNTE) as good as or better than aconventional device.

FIG. 5 illustrates a cross-sectional side view of an intermediatestructure of a SONOS-type device 500 having a scaled ONO stack accordingto an embodiment of the present invention. It should be appreciated thatvarious other SONOS embodiments disclosed herein may also be employed toproduce a scaled ONO stack beyond the specific embodiment depicted inFIG. 5, but nonetheless also operable at a reduced program/erasevoltage. Thus, while the features of FIG. 5 may be referenced throughoutthe description, the present invention is not limited to this particularembodiment.

In the specific embodiment shown in FIG. 5, the SONOS-type device 500includes a SONOS gate stack 502 including an ONO stack 504 formed over asurface 506 of a substrate 508. SONOS-type device 500 further includesone or more source and drain regions 510, aligned to the gate stack 502and separated by a channel region 512. Generally, the scaled SONOS gatestack 502 includes a gate layer 514 formed upon and in contact with thescaled ONO stack 504 and a portion of the substrate 508. The gate layer514 is separated or electrically isolated from the substrate 508 by thescaled ONO stack 504.

In one embodiment, substrate 508 is a bulk substrate comprised of asingle crystal of a material which may include, but is not limited to,silicon, germanium, silicon-germanium or a III-V compound semiconductormaterial. In another embodiment, substrate 508 is comprised of a bulklayer with a top epitaxial layer. In a specific embodiment, the bulklayer is comprised of a single crystal of a material which may include,but is not limited to, silicon, germanium, silicon/germanium, a Ill-Vcompound semiconductor material and quartz, while the top epitaxiallayer is comprised of a single crystal layer which may include, but isnot limited to, silicon, germanium, silicon/germanium and a III-Vcompound semiconductor material. In another embodiment, substrate 508 iscomprised of a top epitaxial layer on a middle insulator layer which isabove a lower bulk layer. The top epitaxial layer is comprised of asingle crystal layer which may include, but is not limited to, silicon(i.e. to form a silicon-on-insulator (SOI) semiconductor substrate),germanium, silicon/germanium and a III-V compound semiconductormaterial. The insulator layer is comprised of a material which mayinclude, but is not limited to, silicon dioxide, silicon nitride andsilicon oxy-nitride. The lower bulk layer is comprised of a singlecrystal which may include, but is not limited to, silicon, germanium,silicon/germanium, a III-V compound semiconductor material and quartz.Substrate 508 and, hence, the channel region 512 between the source anddrain regions 510, may comprise dopant impurity atoms. In a specificembodiment, the channel region is doped P-type and, in an alternativeembodiment, the channel region is doped N-type.

Source and drain regions 510 in substrate 508 may be any regions havingopposite conductivity to the channel region 512. For example, inaccordance with an embodiment of the present invention, source and drainregions 510 are N-type doped while channel region 512 is P-type doped.In one embodiment, substrate 508 is comprised of boron-dopedsingle-crystal silicon having a boron concentration in the range of1×10¹⁵-1×10¹⁹ atoms/cm³. Source and drain regions 510 are comprised ofphosphorous or arsenic doped regions having a concentration of N-typedopants in the range of 5×10¹⁶-5×10¹⁹ atoms/cm³. In a specificembodiment, source and drain regions 510 have a depth in substrate 508in the range of 80-200 nanometers. In accordance with an alternativeembodiment of the present invention, source and drain regions 510 areP-type doped while the channel region of substrate 508 is N-type doped.The SONOS-type device 500 further includes, over channel region 512, agate stack 502 including an ONO stack 504, a gate layer 514 and a gatecap layer 525. The ONO stack 504 further includes tunneling layer 516, acharge trapping layer 518 and a blocking layer 520.

In an embodiment, the tunneling layer 516 includes a nitridized oxide.Because programming and erase voltages produce large electric fieldsacross a tunneling layer, on the order of 10 MV/cm, the program/erasetunneling current is more a function of the tunneling layer barrierheight than the tunneling layer thickness. However, during retention,there is no large electric field present and so the loss of charge ismore a function of the tunneling layer thickness than barrier height. Toimprove tunneling current for reduced operating voltages withoutsacrificing charge retention, in a particular embodiment, the tunnelinglayer 516 is a nitridized oxide. Nitridation increases the relativepermittivity or dielectric constant (e) of the tunneling layer byinducing nitrogen to an otherwise pure silicon dioxide film. In certainembodiments, the tunneling layer 516 of nitridized oxide has the samephysical thickness as a conventional SONOS-type device employing pureoxygen tunnel oxide. In particular embodiments, nitridation provides atunnel layer with an effective (e) between 4.75 and 5.25, preferablybetween 4.90 and 5.1 (at standard temperature). In one such embodiment,nitridation provides a tunnel layer with an effective (e) of 5.07, atstandard temperature.

In certain embodiments, the nitridized tunnel oxide of the scaled SONOSdevice has the same physical thickness as a conventional, non-scaledSONOS device employing pure oxygen tunnel oxide. Generally, the higherpermittivity of the nitridized tunnel oxide results in the memory layercharging faster. In such embodiments, the charge trapping layer 518charges during program/erase faster than a pure oxygen tunnel oxide ofthat thickness because relatively less of the large electric field fromthe control gate is dropped across the nitridized tunnel oxide (due tothe relatively higher permittivity of nitridized tunnel oxide). Theseembodiments allow the SONOS-type device 500 to operate with a reducedprogram/erase voltage while still achieving the same program/erasevoltage threshold level (VTPNTE) as a conventional SONOS-type device. Ina particular embodiment, the SONOS-type device 500 employs a tunnelinglayer 516 having nitridized tunnel oxide with a physical thicknessbetween 1.5 nm and 3.0 nm, and preferably between 1.9 nm and 2.2 nm.

In a further embodiment, the tunneling layer 516 is nitridized in aparticular manner to reduce the trap density at the substrate interfaceto improve charge retention. For particular embodiments in which thenitridized oxide tunneling layer is scaled to be the same physicalthickness as a pure oxygen tunnel oxide, charge retention may beapproximately the same as the pure oxygen tunnel oxide of the samethickness. Referring to FIG. 6, depicting an approximate nitrogenconcentration profile within one embodiment of the tunneling layer 616,the nitrogen concentration 614 decreases rapidly toward the substrateinterface 613 to limit the formation of a silicon nitride (Si2N4) layerin contact with the substrate 612. A silicon nitride layer, comprisingpolar molecules, detrimentally increases the trap density if present atthe substrate interface 613, thereby reducing charge retention via trapto trap tunneling. Thus, by adjusting the nitrogen concentration withinthe nitridized tunnel oxide, the programming/erase Vcg may be reducedwithout a significant reduction in charge retention of the scaled SONOSdevice. As further shown in FIG. 6, 25% of the thickness of thetunneling layer 616 proximate to the interface 613, is nitridized tohave a nitrogen concentration 614 less than about 5×1021 nitrogenatoms/cm3 while 25% of the thickness of the tunneling layer 616proximate to the charge trapping layer 618 is nitridized to have atleast 5×1021 nitrogen atoms/cm3.

In one embodiment, nitridization of oxide within the tunneling layerreduces its energy barrier and increases the dielectric constantrelative to a pure oxide tunneling layer. As shown in FIG. 5, tunnelinglayer 516 is annotated for illustration purposes with a centerline 517.FIG. 6 depicts a similar centerline 617 with one half the thickness ofthe tunneling layer 616 proximate the substrate 612 and one half thethickness of the tunneling layer 616 proximate the charge trapping layer620. In a particular embodiment, the nitrogen concentration 614 is below5×10²¹ atoms/cm³ throughout the first 25% of the thickness of thetunneling layer 616 and reaches approximately 5×10²¹ atoms/cm³ at 50% ofthe thickness of the tunneling layer 616, or at the centerline 617. In afurther embodiment, the nitrogen concentration 614 is above 5×10²¹atoms/cm3 within the last 25% of the thickness of the tunneling layer616, proximate the charge trapping layer 618. In an exemplaryimplementation, for a 2.2 nm tunneling layer, the nitrogen concentration614 is below 5×10²¹ atoms/cm³ within the first 0.6 nm of the tunnelinglayer proximate the substrate 612 and is at least 5×10²¹ atoms/cm³ at1.1 nm of the tunneling layer 616 thickness. In this manner, thecapacitance of the tunneling layer may be increased without asignificant reduction in charge retention of a scaled SONOS-type device.

FIG. 7A illustrates a graph depicting a simulation showing a reductionin programming voltage attributable to a nitridized oxide tunnelinglayer in accordance with an embodiment of the present invention. Asshown, leakage current at retention voltages for 20 Å pure oxidetunneling layer and 40 Å nitride charge trapping layer is equal to 20 Ånitridized oxide tunneling layer and 40 Å charge trapping layer nitride,while charging current for the nitridized oxide tunneling layer atprogramming voltages is greater than that of the pure oxide tunnelinglayer. Thus, at a program or erase voltage of 9.1 V, a nitridized oxidetunneling layer in accordance with the present invention may provide thesame program erase level achieved with a 10 V program or erase voltageand a conventional pure oxide tunneling layer.

Referring back to FIG. 5, the charge trapping layer 518 of theSONOS-type device 500 may further include any commonly known chargetrapping material and have any thickness suitable to store charge and,modulate the threshold voltage of the device. In certain embodiments,charge trapping layer 518 is silicon nitride (SiN₄), silicon-richsilicon nitride, or silicon-rich silicon oxynitride. The silicon-richfilm includes daggling silicon bonds. In one particular embodiment, thecharge trapping layer 518 has a non-uniform stoichiometry across thethickness of charge trapping layer. For example, the charge trappinglayer 518 may further include at least two oxynitride layers havingdiffering compositions of silicon, oxygen and nitrogen. Suchcompositional non-homogeneity within the charge trapping layer has anumber of performance advantages over a conventional SONOS chargetrapping layer having a substantially homogeneous composition. Forexample, reducing the thickness of the conventional SONOS chargetrapping layer increases the trap to trap tunneling rate, resulting in aloss of data retention. However, when the stoichiometry of the chargetrapping layer is modified in accordance with an embodiment of thepresent invention, the thickness of the charge trapping layer may bescaled down while still maintaining good data retention.

In a particular embodiment, the bottom oxynitride layer 518A provides alocal region within the charge trapping layer having a relatively lowerdensity of trap states, thereby reducing the trap density at the tunneloxide interface to reduce trap assisted tunneling in the scaled SONOSdevice. This results in reduced stored charge loss for a given chargetrapping layer thickness to enable scaling of the charge trapping layerfor scaling of the ONO stack EOT. In one such embodiment, the bottomoxynitride 518A has a first composition with a high siliconconcentration, a high oxygen concentration and a low nitrogenconcentration to provide an oxygen-rich oxynitride. This firstoxynitride may have a physical thickness between 2.5 nm and 4.0 nmcorresponding to an EOT of between 1.5 nm and 5.0 nm. In one particularembodiment, the bottom oxynitride layer 518A has an effective dielectricconstant (E) of approximately 6.

In a further embodiment, a top oxynitride layer 518B provides a localregion within the charge trapping layer having a relatively higherdensity of trap states. The relatively higher density of trap statesenables a charge trapping layer of reduced thickness to providesufficient trapped charge that the memory window remains adequate in thescaled ONO stack. Thus, the higher density of trap states has the effectof increasing the difference between programming and erase voltages ofmemory devices for a particular charge trapping layer thickness,allowing the charge trapping layer thickness to be reduced and therebyreducing the EOT of the ONO stack in the scaled SONOS device. In aparticular embodiment, the composition of the top oxynitride layer has ahigh silicon concentration and a high nitrogen concentration with a lowoxygen concentration to produce a silicon-rich, oxygen-lean oxynitride.Generally, the higher silicon content of the top oxynitride, the higherthe density of trap states provided by the top oxynitride and the morethe top oxynitride layer thickness can be reduced (thereby reducing thecharge trapping layer thickness to enable lower voltage operation).Furthermore, the higher the silicon content, the greater thepermittivity and the lower the EOT for the top oxynitride layer. Thisreduction in EOT may more than offset the increase in EOT of theoxygen-rich bottom oxynitride, for a net reduction in EOT of the chargetrapping layer relative to conventional oxynitride charge trappinglayers having a substantially homogeneous composition. In one suchembodiment, the top oxynitride an effective dielectric constant ofapproximately 7.

FIG. 7B depicts exemplary secondary ion mass spectroscopy (SIMS)profiles indicating the concentrations in atoms/cm3 of silicon (Si),nitrogen (N), oxygen (O) and hydrogen (H) after deposition(as-deposited) of a tunneling layer, charge trapping layer, and blockinglayer. A base line condition (“BL”) and a dual-layer oxynitridecondition like that depicted in FIG. 5 (“Bilayer”) are overlaid. Thebaseline condition has a conventional charge trapping layer with ahomogenous composition. The x-axis represents the depth with 0 nm beingat the exposed top surface of the blocking layer and proceeding throughthe stack from top down, terminating in the substrate. As shown, theoxygen concentration for the Bilayer condition is well below 1.0×10²²atoms/cm³ in the depth region between approximately 5 nm and 10 nm,corresponding to a portion of the charge trapping layer. In contrast,the baseline condition displays a substantially higher oxygenconcentration of greater than 1.0×10²² within this same region. Asfurther shown, the baseline condition has a substantially constantoxygen concentration between the 6 nm and 10 nm marks while the Bilayercondition shows substantially more oxygen near the 10 nm mark than the 6nm mark. This non-uniformity in oxygen concentration represents thetransition between the oxygen lean top oxynitride and the oxygen-richbottom oxynitride in the Bilayer condition.

In certain embodiments, the ratio of the bottom oxynitride layerthickness to the top oxynitride layer thickness is between 1:6 and 6:1,and more preferably at the ratio of bottom oxynitride thickness to topoxynitride thickness is at least 1:4. In an exemplary implementationwhere the first oxynitride has a physical thickness between 2.5 nm and4.0 nm, the second oxynitride 518B has a physical thickness between 5.0nm and 6.0 nm for a charge trapping layer 518 with a net physicalthickness of between 7.5 nm and 10.0 nm. In one specific embodiment,employing a bottom oxynitride with a physical thickness of 30 Å, the topoxynitride has a physical thickness of 60 Å for a scaled charge trappinglayer with a net physical thickness of 90 Å.

In these particular embodiments, compositional non-homogeneity isutilized to both locate and confine traps to an embedded locale of thecharge trapping layer (i.e. concentrate the traps) a distance from thetunnel layer interface. FIG. 8A further illustrates an energy banddiagram during retention of a scaled SONOS device including a nitridizedtunnel oxide 816, a multi-layer charge trapping oxynitride 818 and adensified blocking layer 820 between a substrate 812 and control gate814 according to an embodiment of the present invention. As depicted,the non-homogeneity in the composition of the charge trapping layer 818impacts both the valence and conduction bands between the silicon-richtop oxynitride 818B and oxygen-rich bottom oxynitride 818A of the chargetrapping layer. As shown in FIG. 8B, the charge trapping layer inaccordance with an embodiment the present invention provides amodulation in the bands at the interface of the oxygen-rich andsilicon-rich oxynitride layers within the charge trapping layer 818.This band gap modulation serves to locate the trapped charge centroidwithin the top oxynitride layer, further away from the substrate for agiven charge trapping layer thickness. The conduction band modulationbetween the oxynitride layers may also serve to reduce back streaming.

As further shown in FIG. 8A, a portion of the silicon-rich topoxynitride 818B is oxidized or reoxidized in a particular embodiment.Such an oxidation of the silicon rich top region may produce a gradedband gap proximate to the blocking layer 820 relative to thepre-oxidation band gap depicted as dashed lines for illustrationpurposes in FIG. 8A. In an embodiment, approximately half of the topoxynitride layer 818B is reoxidized to have a higher oxygenconcentration toward the interface with the blocking layer 820. Inanother embodiment, substantially all of the top oxynitride layer 818Bis reoxidized to have a higher oxygen concentration than as-deposited.In one embodiment, the reoxidation increases the oxygen concentration inthe top oxynitride layer 818B by approximately 0.25×10²¹-0.35×10²¹atoms/cm. Such embodiments employing a reoxidized charge trapping layermay prevent trap migration to the interface between the charge trappinglayer and the blocking layer, thereby allowing the charge trapping layerthickness to be reduced without incurring the charge retention penaltyassociated with thinning a charge trapping layer of substantiallyhomogeneous composition. Preventing the charge from migrating to theblocking oxide layer also reduces the electric field across the blockingoxide during erase which reduces the back streaming of electrons, or toallow scaling down the blocking oxide while maintaining the same levelof electron back streaming. Such trap location and confinement providedby the regions of distinct stoichiometry in the charge trapping layerand as further combined with reoxidation of a portion of the chargetrapping layer in particular embodiments may enable a scaled SONOSdevice in accordance with the present invention to operate at a reducedvoltage or with faster program and erase times while maintaining goodmemory retention.

Although depicted in the figures and described elsewhere herein ashaving only two oxynitride layers, i.e., a top and a bottom layer, thepresent invention is not so limited, and the multi-layer charge storinglayer can include any number, n, of oxynitride layers, any or all ofwhich having differing compositions of oxygen, nitrogen and/or silicon.In particular, multi-layer charge storing layers having up to fiveoxynitride layers of differing compositions have been produced andtested.

As further depicted in FIG. 5, the blocking layer 520 of the ONO stack504 includes a layer of silicon dioxide between about 30 Å and about 50Å. Scaling of the blocking layer 520 in the ONO stack of the SONOS-typedevice is non-trivial because if done improperly can detrimentallyincrease back streaming of carriers from the control gate under certainbias conditions. In one embodiment including a partially reoxidizedcharge trapping layer, the blocking layer 520 is a high temperatureoxide (HTO) which is relatively denser than as-deposited. A densifiedoxide has a lower fraction of terminal hydrogen or hydroxyl bonds. Forexample, removal of the hydrogen or water from an HTO has the effect ofincreasing the film density and improving the quality of the HTO. Thehigher quality oxide enables the layer to be scaled in thickness. In oneembodiment, the hydrogen concentration is greater than 2.5×1020atoms/cm3 as deposited and is reduced to below 8.0×1019 atoms/cm3 in thedensified film. In an exemplary embodiment, the thickness of the HTO isbetween 2.5 nm and 10.0 nm as-deposited and anywhere between 10% and 30%thinner upon densification.

In an alternate embodiment, the blocking oxide layer is further modifiedto incorporate nitrogen. In one such embodiment, the nitrogen isincorporated in the form of an ONO stack across the thickness of theblocking oxide layer. Such a sandwich structure in place of theconventional pure oxygen blocking layer advantageously reduces the EOTof the entire stack between the channel and control gate as well asenable tuning of band offsets to reduce back injection of carriers. TheONO block layer can then be incorporated with the nitridized tunneloxide and charge trapping layer comprising a bottom oxynitride layer anda top oxynitride layer.

Over the ONO stack 504 is a gate layer 514. The gate layer 514 may beany conductor or semiconductor material. In one such embodiment, thegate layer 514 is polysilicon (poly). In another embodiment, the gatelayer 514 contains a metal, such as, but not limited to, hafnium,zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum,cobalt and nickel, their silicides, their nitrides and their carbides.In one particular embodiment, the gate layer 514 is poly-silicon havinga physical thickness of between 70 nm and 250 nm.

As further shown in FIG. 5, the SONOS-type device 500 includes a gatecap layer 525 super adjacent to the gate layer 514 and has approximatelythe same critical dimensions as the gate layer 514 and ONO stack 504. Incertain embodiments, the gate cap layer 525 forms the top layer of thegate stack 502 and provides a hard mask during patterning of the gatelayer 514 and ONO stack 504. In some embodiments, the gate cap layer 525facilitates formation of self-aligned contacts (SAC) to the SONOSdevices. The gate cap layer 525 may be comprised of any material capableproviding the necessary selectivity to subsequent etch processes, suchas, but not limited to, silicon dioxide, silicon nitride and siliconoxynitride.

In one specific embodiment, a SONOS-type device employs an ONO stackincluding a nitridized tunnel oxide with an EOT of 14 Å corresponding toa physical thickness of approximately 18 Å, a charge trapping layercomprising a bottom oxynitride layer with an EOT of 20 Å correspondingto a physical thickness of approximately 25 Å and a top oxynitride layerwith an EOT of 30 Å corresponding to a physical thickness ofapproximately 60 Å, and a blocking oxide layer deposited to 40 Å anddensified to 30 Å. Such a SONOS-type device may be operated at a voltagerange of approximately 9 V, to provide an initial erase voltagethreshold level (VTE) of −2 V after a 1 ms to 10 ms pulse.

FIG. 9 depicts a flow chart of a method for fabricating a scaled SONOS,such as that depicted in FIG. 5, including a nitridized oxide tunnelinglayer, a multi-layer charge trapping oxynitride that has been partiallyreoxidized and a densified blocking oxide layer, as described above. Thefabrication method of FIG. 9 begins with forming a nitridized oxidetunneling layer over a silicon-containing surface of a substrate atoperation 900. FIG. 10 depicts a flow chart of specific method forforming the nitridized oxide of operation 900 in FIG. 9.

In the embodiment depicted in FIG. 10, tailoring of the nitrogen profilein the nitridized tunnel oxide of a SONOS-type device is accomplishedwith a multi-step nitridation and oxidation method. At operation 1001, athin thermal oxide is formed from a silicon containing layer on asurface of a substrate, such as substrate 508 of FIG. 5. Because a goodinterface with the substrate is necessary, formation of a chemical oxidemay preface the thermal oxidation. In a particular embodiment,therefore, a chemical oxide is present during the thermal oxidation (asopposed to performing a conventional “HF last” preclean). In one suchembodiment, the chemical oxide is grown with ozonated water to form achemical oxide layer with a thickness of approximately 1.0 nm.

The thermal oxide is formed to a thickness of between approximately 1.0nm and 1.8 nm. In a particular embodiment, the thermal oxide is formedto a thickness of between 1.0 nm and 1.2 nm. Thus, in embodiments wherea 1.0 nm chemical oxide is present during the thermal oxidation ofoperation 501, the thickness of the surface oxide does not substantiallyincrease, however the quality of the oxide is improved. In a furtherembodiment, the oxide is of relatively low density to facilitatesubsequent incorporation of a significant wt % of nitrogen. Too low of afilm density, however, will result in too much nitrogen at the siliconsubstrate interface. Formation of the silicon dioxide layer at operation1001 further serves as a means to block additional substrate oxideformation during subsequent thermal processing, discussed further below.In one embodiment, an atmospheric pressure vertical thermal reactor(VTR) is employed to grow the thermal oxide at a temperature between680° C. and 800° C. in the presence of an oxidizing gas such as, oxygen(O₂), nitrous oxide (N₂O), nitric oxide (NO), ozone (O₃), and steam(H₂O). Depending on the oxidizer chosen, the oxidation of operation 1001may be from 3.5 minutes to 20 minutes in duration. In one atmosphericembodiment, employing O₂ gas at a temperature between 700° C. and 750°C., a process time between 7 minutes and 20 minutes forms anapproximately 1.0 nm silicon dioxide film.

In another embodiment, the oxidation operation 1001 is performed with asub-atmospheric processor such as the Advanced Vertical Processor (AVP)commercially available from AVIZA technology of Scotts Valley, Calif.The AVP may be operated in the temperature range described above for aVTR embodiment and at a pressure between 1 Torr (T) and atmosphericpressure. Depending on the operating pressure, the oxidation time toform a thermal silicon dioxide film of between approximately 1.0 nm and1.8 nm in thickness may extend up to nearly an hour, as may bedetermined by one of ordinary skill in the art.

Next, at operation 1002 in the multiple oxidation nitridation methodembodiment depicted in FIG. 10, the thermal oxide formed at operation1001 is nitridized. Generally, at operation 1002, a nitrogen anneal isperformed to increase the dielectric constant (K) and reduce the fixedcharge of the thermal oxide layer. In one embodiment, the nitrogenanneal employs nitrogen (N₂) or a hydrogenated nitrogen source, such asammonia (NH₃). In another embodiment, the nitrogen anneal employs adeuterated nitrogen source, such as deuterated ammonia (ND₃). In onespecific embodiment, the nitrogen anneal is performed at a temperaturebetween 700° C. and 850° C. for between 3.5 minutes and 30 minutes. Inanother specific embodiment, the nitrogen anneal is performed at atemperature between 725° C. and 775° C., for between 3.5 minutes and 30minutes. In one such embodiment, NH₃ is introduced at atmosphericpressure at a temperature of between 725° C. and 775° C., for between3.5 minutes and 30 minutes. In an alternative embodiment, a subatmospheric NH₃ anneal is performed at 800° C. to 900° C. for 5 minutesto 30 minutes in a processor such as the AVP. In still otherembodiments, commonly known nitrogen plasma and thermal annealcombinations are performed.

Following operation 1002, a reoxidation is performed at operation 1004.In one embodiment, during the reoxidation process, an oxidizing gas isthermally cracked to provide oxygen radicals close to the film surface.The oxygen radicals eliminate nitrogen and hydrogen trap charge. Thereoxidation operation 1004 also grows an additional oxide at thesubstrate interface to provide a physical offset between the substrateand a nitrogen concentration within the tunneling layer. For example,referring back to FIG. 5, the reoxidation helps to separate thesubstrate interface 513 from a nitrogen concentration within thetunneling layer 516. As specifically shown in FIG. 6, for oneimplementation, the nitrogen concentration 614 in the tunneling layer616 at the substrate interface 613 is significantly below 5×10²¹atoms/cm³ and may be on the order of 5×10²⁰ atoms/cm³. This offset inthe nitrogen from the substrate interface improves retention of aSONOS-type device. In one embodiment, the thickness of the oxide grownat the substrate interface 613 is limited to between 1.2 nm and 3.0 nm.At operation 1004, the reoxidation process conditions are chosen suchthat the thickness of the thermal oxide formed at operation 1001prevents oxidation beyond a thickness of approximately 3.0 nm, whichcould render a tunneling layer devoid of any advantageous nitrogenconcentration. Commonly known oxidizers may be employed for thereoxidation process, such as, but not limited to, NO, N₂O, O₂, O₃ andsteam. Any such oxidizers may be introduced with known thermalprocessors operating at a temperature of between 800° C. and 850° C.Depending on the operating parameters, reoxidation time may be anywherebetween 5 minutes and 40 minutes. In a particular embodiment, NO isemployed in an atmospheric furnace operated at a temperature between800° C. and 850° C. for a process time of approximately 15 minutes toform a nitridized oxide film that is approximately 2.2 nm in thicknesson a silicon substrate. In one such embodiment, the reoxidized film 2.2nm thick forms a region between 0.5 nm and 0.8 nm proximate to theinterface with the silicon substrate, the region having a nitrogenconcentration below 5×10²¹ atoms/cm³.

Following the reoxidation of operation 1004, a second nitrogen anneal isperformed at operation 1006 to renitridize the tunneling layer. A secondnitrogen anneal is employed to further increase the dielectric constantof the tunneling layer without detrimentally introducing a large numberof hydrogen or nitrogen traps at the substrate interface. In oneembodiment, the second nitrogen anneal of operation 1006 is performedwith conditions identical to the anneal performed in operation 1002. Inanother embodiment, the second nitrogen anneal of operation 1006 isperformed at a higher temperature than the first nitrogen anneal ofoperation 1002 to introduce additional nitrogen into the tunnelinglayer. In one embodiment, the nitrogen anneal employs a hydrogenatednitrogen source, such as NH₃ In another embodiment, the nitrogen annealemploys a deuterated nitrogen source, such as ND₃. In a specificembodiment, the nitrogen anneal of operation 1006 employs NH₃ atatmospheric pressure and a temperature between 750° C. and 950° C. witha processing time of between 3.5 minutes and 30 minutes. In anotherparticular embodiment, the NH₃ anneal is performed at atmosphericpressure between 800° C. and 850° C. for between 5 minutes and 10minutes.

As described, operations 1001 through 1006 depicted in FIG. 10 providetwo oxidation operations and two nitridation operations. The iterativeoxidation, nitridation scheme depicted enables specific tailoring of thenitrogen concentration in the tunneling layer to achieve both areduction in programming voltage or increase in programming speed and anincrease in memory retention of a SONOS-type device. The successivenature of the oxidation, nitridation, reoxidation, renitridationoperations 1001-1006 enable an appreciable nitrogen concentration in atunneling layer less than 3.0 nm thick while providing an interfacebetween the tunneling layer and the substrate that has very littlenitrogen and hydrogen traps. The independent oxidation, nitridation,reoxidation, renitridation operations 1001-1006 enable the first andsecond oxidations and first and second nitridation to be performed withindependently engineered conditions to provide greater degrees offreedom in tailoring the nitrogen concentration profile in a tunnelinglayer. In one advantageous embodiment, operation 1001, 1002, 1004 and1006 are successively performed in a single thermal processor withoutremoving the substrate from the processor between operations. In onesuch embodiment, process pressure is held at atmosphere for operations1001-1006. First, oxidation operation 1001 is performed at a temperatureof between 700° C. and 750° C. Gas flows are then modified as prescribedto perform the nitrogen anneal of operation 1002 at a temperaturebetween 725° C. and 775° C. The furnace temperature is then ramped up tobetween 800° C. and 850° C. and gas flows are again modified to performthe reoxidation of operation 1004. Finally, while holding the furnacebetween 800° C. and 850° C., gas flows are again modified to perform thesecond nitrogen anneal of operation 1006.

With the nitridized oxide tunneling layer 516 of FIG. 5 substantiallycomplete, fabrication of the ONO stack may continue by returning to themethod depicted in FIG. 9. In one embodiment, multiple nitride oroxynitride charge trapping layers are formed at operations 902 and 904in a low pressure chemical vapor deposition (CVD) process using asilicon source, such as silane (SiH₄), dichlorosilane (SiH₂Cl₄),tetrachlorosilane (SiCl₄) or BisTertiaryButylAmino Silane (BTBAS), anitrogen source, such as N₂, NH₃, N₂O or nitrogen trioxide (NO₃), and anoxygen-containing gas, such as O₂ or N₂O. Alternatively, gases in whichhydrogen has been replaced by deuterium can be used, including, forexample, the substitution of ND₃ for NH₃ The substitution of deuteriumfor hydrogen advantageously passivates Si dangling bonds at thesubstrate interface, thereby increasing an NBTI (Negative BiasTemperature Instability) lifetime of SONOS-type devices.

In one exemplary implementation, an oxynitride charge trapping layer canbe deposited at operation 902 over a tunneling layer by placing thesubstrate in a deposition chamber and introducing a process gasincluding N₂O, NH₃ and DCS, while maintaining the chamber at a pressureof from about 5 millitorr (mT) to about 500 mT, and maintaining thesubstrate at a temperature of from about 700° C. to about 850° C. andmore preferably at least about 780° C., for a period of from about 2.5minutes to about 20 minutes. In a further embodiment, the process gascan include a first gas mixture of N₂O and NH₃ mixed in a ratio of fromabout 8:1 to about 1:8 and a second gas mixture of SiH₂Cl₂ and NH₃ mixedin a ratio of from about 1:7 to about 7:1, and can be introduced at aflow rate of from about 5 to about 200 standard cubic centimeters perminute (sccm). It has been found that an oxynitride layer produced ordeposited under these condition yields a silicon-rich oxygen-rich,oxynitride layer, such as the charge trapping layer 518A depicted inFIG. 5. Formation of the charge trapping layer may further involve a CVDprocess at operation 904 employing a first gas mixture of N₂O and NH₃mixed in a ratio of from about 8:1 to about 1:8 and a second gas mixtureof SiH₂Cl₂ and NH₃ mixed in a ratio of from about 1:7 to about 7:1,introduced at a flow rate of from about 5 to about 20 seem to yield asilicon-rich, nitrogen-rich, and oxygen lean oxynitride layer, such asthe charge trapping layer 518B depicted in FIG. 5.

In one embodiment, formation of a charge trapping layer at operations902 and 904 is performed sequentially in the same processing tool usedto form the tunneling layer without unloading the substrate from thedeposition chamber between operations 900 and 904. In a specificembodiment, the charge trapping layer is deposited without altering thetemperature at which the substrate was heated during the second nitrogenanneal of operation 1006 of FIG. 10. In one embodiment, the chargetrapping layer is deposited sequentially and immediately followingnitridation of the tunneling layer at operation 900 by modifying theflow rate of NH₃ gas, and introducing N₂O and SiH₂Cl₂ to provide thedesired gas ratios to yield either a silicon-rich and oxygen-rich layer,a silicon-rich and nitrogen-rich oxynitride layer, or both layers in adual-layer implementation.

Following operation 904, a blocking layer can be formed at operation 906by any suitable means including, for example, thermal oxidation ordeposition with CVD techniques. In a preferred embodiment, the blockinglayer is formed with a high-temperature CVD process. Generally, thedeposition process involves providing a silicon source, such as SiH₄,SiH₂Cl, or SiCl₄ and an oxygen-containing gas, such as O₂ or N₂O in adeposition chamber at a pressure of from about 50 mT to about 1000 mT,for a period of from about 10 minutes to about 120 minutes whilemaintaining the substrate at a temperature of from about 650° C. toabout 850° C. Preferably, the blocking layer is deposited sequentiallyin the same processing tool employed to form the charge trappinglayer(s) at operations 902 and 904. More preferably, the blocking layeris formed in the same processing tool as is both the charge trappinglayer(s) and the tunneling layer without removing the substrate betweenoperations.

In the embodiment depicted in FIG. 9, the blocking layer deposited atoperation 906 is reoxidized at operation 907 to densify the blockinglayer oxide. As discussed elsewhere herein, operation 907 may furtheroxidize or reoxidize a portion or all of the charge trapping layer, suchas a portion or all of the charge trapping layer 518B shown in FIG. 5 toachieve a graded band gap, such as depicted in FIG. 8A. Generally, thereoxidation may be performed in the presence of an oxidizing gas suchas, oxygen (O₂), nitrous oxide (N₂O), nitric oxide (NO), ozone (O₃), andsteam (H₂O). In one embodiment, the reoxidation process may is performedat a higher temperature than the temperature at which the blocking layeris deposited. Reoxidation after the deposition of the blocking oxideenables a more controlled diffusion of oxidizer to controllably oxidizeor reoxidize the thin charge trapping layer. In a particularlyadvantageous embodiment, a dilute wet oxidation is employed. The dilutewet oxidation is distinct from a wet oxidation in that the H₂:O₂ ratiois between 1 and 1.3. In one specific embodiment, a dilute oxidationwith an H₂:O₂ ratio of approximately 1.2 is performed at a temperatureof between 800° C. and 900° C. In a further embodiment, the duration ofthe dilute oxidation may be sufficient to grow between 5.0 nm and 12.5nm of silicon dioxide on a silicon substrate. In one such embodiment,the duration is sufficient to for an approximately 10 nm to 1.1 nmsilicon dioxide layer on a silicon substrate. Such a dilute oxidationprocess serves to reoxidize the deposited blocking layer oxide and mayfurther oxidize or reoxidize a portion of the charge trapping layer toimpart a band structure like that depicted in FIG. 8A or 8B. In anotherembodiment, the reoxidation of operation 907 may further serve to form agate oxide in a non-SONOS-type device region, such as for acomplementary metal oxide silicon (CMOS) field effect transistors (FET),on the same substrate as the SONOS-type device. In another embodiment,the reoxidation of operation 907 may further serve to diffuse deuteriuminto portions of the charge trapping layer or blocking layer of theSONOS-type device.

As depicted in FIG. 9, the method may then be completed at operation 908with formation of a gate layer, such as the gate layer 514 of FIG. 5. Incertain embodiments, operation 908 may further include formation of agate cap layer, such as gate cap layer 525 depicted in FIG. 5. With thecompletion of the gate stack fabrication, further processing may occuras known in the art to conclude fabrication of the SONOS-type device300.

Although the present invention has been described in language specificto structural features and/or methodological acts, it is to beunderstood that the invention defined in the appended claims is notnecessarily limited to the specific features or acts described. Thespecific features and acts disclosed are to be understood asparticularly graceful implementations of the claimed invention in aneffort to illustrate rather than limit the present invention.

Implementations and Alternatives

FIG. 11 illustrates a cross-sectional side view of an intermediatestructure of a SONOS-type memory device 1100 having a scaled ONOstructure including a nitridized oxide tunneling layer, a multi-layercharge trapping layer and a densified blocking layer. It should beappreciated that various other SONOS embodiments disclosed herein mayalso be employed to produce a scaled ONO stack beyond the specificembodiment depicted in FIG. 11, but nonetheless also operable at areduced program/erase voltage. Thus, while the features of FIG. 11 maybe referenced throughout the description, the present invention is notlimited to this particular embodiment.

In the specific embodiment shown in FIG. 11, the SONOS-type memorydevice 1100 includes a SONOS gate stack 1102 including an ONO stack 1104formed over a surface 1106 of a substrate 1108. SONOS-type memory device1100 further includes one or more source and drain regions 1110, alignedto the gate stack 1102 and electrically connected by a channel region1112. Generally, the scaled SONOS gate stack 1102 further includes agate layer 1114 formed upon and in contact with the scaled ONO stack1104 and a gate cap layer 1125 over the gate layer 1114. The gate layer1114 is separated or electrically isolated from the substrate 1108 bythe scaled ONO stack 1104.

In one embodiment, substrate 1108 is a bulk substrate comprised of asingle crystal of a material which may include, but is not limited to,silicon, germanium, silicon-germanium or a III-V compound semiconductormaterial. In another embodiment, substrate 1108 is comprised of a bulklayer with a top epitaxial layer. In a specific embodiment, the bulklayer is comprised of a single crystal of a material which may include,but is not limited to, silicon, germanium, silicon/germanium, a III-Vcompound semiconductor material and quartz, while the top epitaxiallayer is comprised of a single crystal layer which may include, but isnot limited to, silicon, germanium, silicon/germanium and a III-Vcompound semiconductor material. In another embodiment, substrate 1108is comprised of a top epitaxial layer on a middle insulator layer whichis above a lower bulk layer. The top epitaxial layer is comprised of asingle crystal layer which may include, but is not limited to, silicon(i.e. to form a silicon-on-insulator (SOI) semiconductor substrate),germanium, silicon/germanium and a III-V compound semiconductormaterial. The insulator layer is comprised of a material which mayinclude, but is not limited to, silicon dioxide, silicon nitride andsilicon oxy-nitride. The lower bulk layer is comprised of a singlecrystal which may include, but is not limited to, silicon, germanium,silicon/germanium, a III-V compound semiconductor material and quartz.Substrate 1108 and, hence, the channel region 1112 between the sourceand drain regions 1110, may comprise dopant impurity atoms. The channelregion 1112 can comprise polysilicon or recrystallized polysilicon toform a monocrystalline channel region. In a specific embodiment, wherethe channel region 1112 includes a monocrystalline silicon, the channelregion can be formed to have <100> surface crystalline orientationrelative to a long axis of the channel region.

Source and drain regions 1110 in substrate 1108 may be any regionshaving opposite conductivity to the channel region 1112. For example, inaccordance with an embodiment of the present invention, source and drainregions 1110 are N-type doped while channel region 1112 is P-type doped.In one embodiment, substrate 1108 is comprised of boron-dopedsingle-crystal silicon having a boron concentration in the range of1×10¹⁵-1×10¹⁹ atoms/cm. Source and drain regions 1110 are comprised ofphosphorous or arsenic doped regions having a concentration of N-typedopants in the range of 5×10¹⁶-5×10¹⁹ atoms/cm³. In a specificembodiment, source and drain regions 1110 have a depth in substrate 1108in the range of 80-200 nanometers. In accordance with an alternativeembodiment of the present invention, source and drain regions 1110 areP-type doped while the channel region of substrate 1108 is N-type doped.

The ONO stack 1104 includes a tunneling layer 1116, a multi-layer chargetrapping layer 1118 and a blocking layer 1120.

In one embodiment, the tunneling layer 1116 is a nitridized oxidetunneling layer including a nitridized oxide. Because programming anderase voltages produce large electric fields across a tunneling layer,on the order of 10 MV/cm, the program/erase tunneling current is more afunction of the tunneling layer barrier height than the tunneling layerthickness. However, during retention, there is no large electric fieldpresent and so the loss of charge is more a function of the tunnelinglayer thickness than barrier height. Nitridation increases the relativepermittivity or dielectric constant (e) of the tunneling layer improvingtunneling current for reduced operating voltages. In particularembodiments, nitridation provides a tunneling layer 1116 with aneffective e between 4.75 and 5.25, and preferably between 4.90 and 5.1(at standard temperature). In one such embodiment, nitridation providesa tunneling layer with an effective a of 5.07, at standard temperature.

In such embodiments, the multi-layer charge trapping layer 1118 chargesfaster during program/erase than a pure oxide tunneling layer of thatthickness because relatively less of the large electric field from thecontrol gate is dropped across the nitridized oxide tunneling layer (dueto the relatively higher permittivity of nitridized tunnel oxide). Theseembodiments allow the SONOS-type memory device 1100 to operate with areduced program/erase voltage while still achieving the sameprogram/erase voltage threshold level (VTPNTE) as a conventionalSONOS-type device.

In some embodiments, the nitridized oxide tunneling layer has the samephysical thickness as a conventional, SONOS device employing pure oxidetunneling layer to improve tunneling current for reduced operatingvoltages without sacrificing charge retention. In certain embodiments,the SONOS-type memory device 1100 employs a nitridized oxide tunnelinglayer 1116 having a thickness of between 1.5 nm and 3.0 nm, and morepreferably between 1.9 nm and 2.2 nm. In a particular embodiment, shownin FIG. 11B, the nitridized oxide tunneling layer 1116 includes a firstregion 1116A proximate to the channel region 1112 having a nitrogenconcentration less than about 5×10²¹ nitrogen atoms/cm³, and a secondregion 1116B proximate to the multi-layer charge trapping layer 1118having a nitrogen concentration at least 5×10²¹ nitrogen atoms/cm³. Inone embodiment shown in FIG. 11B, the first and second regions of thenitridized oxide tunneling layer 1116 each comprise no more thanapproximately 25% of the tunneling layer thickness.

In a further embodiment, the multi-layer charge trapping layer 1118includes at least two layers having differing compositions of silicon,oxygen and nitrogen. In one embodiment, the multi-layer charge-trappingregion includes an oxygen-rich first layer 1118A comprising asubstantially trap-free, silicon-rich, oxygen-rich nitride and anoxygen-lean second layer 1118B comprising a trap-dense, silicon-rich,nitrogen-rich, and oxygen-lean nitride. It has been found that theoxygen-rich first layer 1118A decreases the charge loss rate afterprogramming and after erase, which is manifested in a small voltageshift in the retention mode. The oxygen-lean second layer 1118B improvesthe speed and increases of the initial difference between program anderase voltage without compromising a charge loss rate of memory devicesmade using an embodiment of the silicon-oxide-oxynitride-oxide-siliconstructure, thereby extending the operating life of the device.

In another embodiment the multi-layer charge trapping layer 1118 is asplit multi-layer charge trapping layer further including anintermediate oxide or anti-tunneling layer 1118C comprising an oxideseparating the oxygen-rich first layer 1118A from the oxygen-lean secondlayer 1118B. During an erase of the SONOS-type memory device 1100 holesmigrate toward the blocking layer 1120, but the majority of trapped holecharges form in the oxygen-lean second layer 1118B. Electron chargeaccumulates at the boundaries of the oxygen-lean second layer 1118Bafter programming, and thus there is less accumulation of charge at thelower boundary of the oxygen-rich first layer 1118A. Furthermore, due tothe anti-tunneling layer 1118C, the probability of tunneling by trappedelectron charges in the oxygen-lean second layer 1118B is substantiallyreduced. This may result in lower leakage current than for theconventional memory devices.

Although shown and described above as having two nitride layers, i.e., afirst and a second layer, the present invention is not so limited, andthe multi-layer charge trapping layer 1118 may include a number, n, ofoxide, nitride or oxynitride layers, any or all of which may havediffering stoichiometric compositions of oxygen, nitrogen and/orsilicon. In particular, multi-layer charge storing structures having upto five, and possibly more, nitride layers each with differingstoichiometric compositions are contemplated. At least some of theselayers will be separated from the others by one or more relatively thinoxide layers. However, as will be appreciated by those skilled in theart it is generally desirable to utilize as few layers as possible toaccomplish a desired result, reducing the process steps necessary toproduce the device, and thereby providing a simpler and more robustmanufacturing process. Moreover, utilizing as few layers as possiblealso results in higher yields as it is simpler to control thestoichiometric composition and dimensions of the fewer layers.

In another embodiment, the blocking layer 1120 comprises a hightemperature oxide (HTO) which is relatively denser than as-deposited. Adensified HTO has a lower fraction of terminal hydrogen or hydroxylbonds. For example, removal of the hydrogen or water from an HTO has theeffect of increasing the film density and improving the quality of theHTO. The higher quality oxide enables the layer to be scaled inthickness. In one embodiment, the hydrogen concentration is greater than2.5×1020 atoms/cm3 as deposited and is reduced to below 8.0×1019atoms/cm3 in the densified film. In an exemplary embodiment, thethickness of the blocking layer 1120 comprising a densified HTO isbetween 2.5 nm and 10.0 nm as-deposited and anywhere between 10% and 30%thinner upon densification.

In an alternate embodiment, the blocking layer 1120 is further modifiedto incorporate nitrogen. In one such embodiment, the nitrogen isincorporated in the form of an ONO stack across the thickness of theblocking layer 1120. Such a sandwich structure in place of theconventional pure oxygen blocking layer advantageously reduces the EOTof the entire stack between the channel region 1112 and control gate1114 as well as enable tuning of band offsets to reduce back injectionof carriers. The ONO stack blocking layer 1120 can then be incorporatedwith the nitridized oxide tunneling layer 1116 and split multi-layercharge trapping layer 1118 comprising an oxygen-rich first layer 1118A,an oxygen-lean second layer 118B and an anti-tunneling layer 1118C.

A method or forming or fabricating a memory device including anitridized oxide tunneling layer, a split multi-layer charge trappinglayer and a densified blocking layer according to one embodiment willnow be described with reference to the flowchart of FIG. 12.

Referring to FIG. 12, the method begins at operation 1200 with forming achannel region comprising polysilicon in or on a surface of a substrate,the channel region electrically connecting a source region and a drainregion in the substrate. As noted above, the channel region may compriseP-type or N-type dopant impurity atoms. In a specific embodiment, thechannel region is doped and, in an alternative embodiment, the channelregion is doped. The source and drain regions may be doped with oppositetype dopant impurity atoms to the channel region. For example, inaccordance with one specific embodiment, the source and drain regionsare N-type doped with phosphorous or arsenic doped regions having aconcentration in the range of 5×10¹⁶-5×10¹⁹ atoms/cm³, while the channelregion is P-type doped with boron having a concentration in the range of1×10¹⁵-1×10¹⁹ atoms/cm³.

At operation 1202, a tunneling layer comprising a nitridized oxide isformed on the substrate over the channel region. Generally, thetunneling layer comprising a nitridized oxide is formed by thermallyoxidizing the substrate to form an oxide film followed by nitridizingthe oxide film. Because a good interface with the substrate isnecessary, formation of the thermal oxidation may be preceded byformation of a chemical oxide. In a particular embodiment, a chemicaloxide is grown with ozonated water to form a chemical oxide layer with athickness of approximately 1.0 nm. The thermal oxide is then formed to athickness of between approximately 1.0 nm and 1.8 nm. Preferably, theoxide is of relatively low density to facilitate subsequentincorporation of a significant wt % of nitrogen. Too low of a filmdensity, however, will result in too much nitrogen at the siliconsubstrate interface. In one embodiment, an atmospheric pressure verticalthermal reactor (VTR) is employed to grow the thermal oxide at atemperature between 680° C. and 800° C. in the presence of an oxidizinggas such as, oxygen (O₂), nitrous oxide (N₂O), nitric oxide (NO), ozone(O₃), and steam (H₂O). Depending on the oxidizer chosen, the oxidationof operation 1001 may be from 3.5 minutes to 20 minutes in duration. Inone atmospheric embodiment, employing O₂ gas at a temperature between700° C. and 750° C., a process time between 7 minutes and 20 minutesforms an approximately 1.0 nm silicon dioxide film.

In another embodiment, the thermal oxide is formed with asub-atmospheric processor such as the Advanced Vertical Processor (AVP)commercially available from AVIZA technology of Scotts Valley, Calif.The AVP may be operated in the temperature range described above for aVTR embodiment and at a pressure between 1 Torr (T) and atmosphericpressure. Depending on the operating pressure, the oxidation time toform a thermal silicon dioxide film of between approximately 1.0 nm and1.8 nm in thickness may extend up to nearly an hour, as may bedetermined by one of ordinary skill in the art.

Next, a nitrogen anneal is performed to nitridize the thermal toincrease the dielectric constant (K) and reduce the fixed charge of thethermal oxide layer. In one embodiment, the nitrogen anneal employsnitrogen (N₂) or a hydrogenated nitrogen source, such as ammonia (NH₃).In another embodiment, the nitrogen anneal employs a deuterated nitrogensource, such as deuterated ammonia (ND₃). In one specific embodiment,the nitrogen anneal is performed at a temperature between 700° C. and850° C. for between 3.5 minutes and 30 minutes. In another specificembodiment, the nitrogen anneal is performed at a temperature between725° C. and 775° C., for between 3.5 minutes and 30 minutes. In one suchembodiment, NH₃ is introduced at atmospheric pressure at a temperatureof between 725° C. and 775° C., for between 3.5 minutes and 30 minutes.In an alternative embodiment, a sub atmospheric NH₃ anneal is performedat 800° C. to 900° C. for 5 minutes to 30 minutes in a processor such asthe AVP. In still other embodiments, commonly known nitrogen plasma andthermal anneal combinations are performed.

Optionally, forming the nitridized oxide tunneling layer furtherincludes reoxidizing the oxide film by exposing the substrate to O₂, andrenitridizing the reoxidized nitridized oxide film by exposing thesubstrate the nitridized oxide film to NO. In one embodiment, during thereoxidation process, an oxidizing gas is thermally cracked to provideoxygen radicals close to the film surface. The oxygen radicals eliminatenitrogen and hydrogen trap charge. The reoxidation process also grows anadditional oxide at an interface between the substrate and the tunnelinglayer to provide a physical offset between the substrate and a nitrogenconcentration within the tunneling layer. For example, referring back toFIGS. 11A and 11B, in one embodiment the nitrogen concentration in thetunneling layer 1116A is significantly below that of in the tunnelinglayer 1116B. This offset in the nitrogen from the substrate interfaceimproves retention of a SONOS-type device. In one embodiment, thethickness of the oxide grown at the substrate interface is limited tobetween 1.2 nm and 3.0 nm. In the reoxidation process conditions arechosen such that the thickness of the thermal oxide formed at operation1001 prevents oxidation beyond a thickness of approximately 3.0 nm,which could render a tunneling layer devoid of any advantageous nitrogenconcentration. Commonly known oxidizers may be employed for thereoxidation process, such as, but not limited to, NO, N₂O, O₂, O₃ andsteam. Any such oxidizers may be introduced with known thermalprocessors operating at a temperature of between 800° C. and 850° C.Depending on the operating parameters, reoxidation time may be anywherebetween 5 minutes and 40 minutes. In a particular embodiment, NO isemployed in an atmospheric furnace operated at a temperature between800° C. and 850° C. for a process time of approximately 15 minutes toform a nitridized oxide film that is approximately 2.2 nm in thicknesson a silicon substrate. In one such embodiment, the reoxidized film 2.2nm thick forms a region between 0.5 nm and 0.8 nm proximate to theinterface with the silicon substrate, the region having a nitrogenconcentration below 5×10²¹ atoms/cm³.

Following the reoxidation operation, a second nitrogen anneal isperformed to renitridize the tunneling layer. A second nitrogen annealis employed to further increase the dielectric constant of the tunnelinglayer without detrimentally introducing a large number of hydrogen ornitrogen traps at the substrate interface. In one embodiment, the secondnitrogen anneal of is performed with conditions identical to the initialor first nitrogen anneal. In another embodiment, the second nitrogenanneal of the renitridization operation is performed at a highertemperature than the first nitrogen anneal to introduce additionalnitrogen into the tunneling layer. In one embodiment, the nitrogenanneal employs a hydrogenated nitrogen source, such as NH₃ In anotherembodiment, the nitrogen anneal employs a deuterated nitrogen source,such as ND₃. In a specific embodiment, the second nitrogen annealemploys NH₃ at atmospheric pressure and a temperature between 750° C.and 950° C. with a processing time of between 3.5 minutes and 30minutes. In another particular embodiment, the NH₃ anneal is performedat atmospheric pressure between 800° C. and 850° C. for between 5minutes and 10 minutes.

As described, operation 1202 and the reoxidization and renitridizationprovide two oxidation operations and two nitridation operations. Theiterative oxidation, nitridation scheme depicted enables specifictailoring of the nitrogen concentration in the tunneling layer toachieve both a reduction in programming voltage or increase inprogramming speed and an increase in memory retention of a SONOS-typememory device. The successive nature of the oxidation, nitridation,reoxidation, renitridation operations enable an appreciable nitrogenconcentration in a tunneling layer less than 3.0 nm thick whileproviding an interface between the tunneling layer and the substratethat has very little nitrogen and hydrogen traps. The independentoxidation, nitridation, reoxidation, renitridation operations enable thefirst and second oxidations and first and second nitridation to beperformed with independently engineered conditions to provide greaterdegrees of freedom in tailoring the nitrogen concentration profile in atunneling layer. In one advantageous embodiment, operations aresuccessively performed in a single thermal processor without removingthe substrate from the processor between operations. In one suchembodiment, process pressure is held at atmosphere. The first oxidationoperation is performed at a temperature of between 700° C. and 750° C.Gas flows are then modified as prescribed to perform the nitrogen annealof operation at a temperature between 725° C. and 775° C. The furnacetemperature is then ramped up to between 800° C. and 850° C. and gasflows are again modified to perform the reoxidation operation. Finally,while holding the furnace between 800° C. and 850° C., gas flows areagain modified to perform the second nitrogen anneal operation.

In operation 1204 a multi-layer charge trapping layer is formed on thenitridized oxide tunneling layer. Generally, the multi-layer chargetrapping layer includes a substantially trap free, oxygen-rich firstlayer, and a trap dense oxygen-lean second layer. In certainembodiments, the multi-layer charge trapping layer is a splitmulti-layer charge trapping layer further including an anti-tunnelinglayer comprising an oxide separating the first layer from the secondlayer.

In a particular embodiment, the oxygen-rich first layer is formed ordeposited in a low pressure CVD process using a silicon source, such assilane (SiH₄), chlorosilane (SiH₃Cl), dichlorosilane or DCS (SiH₂Cl₂),tetrachlorosilane (SiCl₄) or Bis-TertiaryButylAmino Silane (BTBAS), anitrogen source, such as nitrogen (N₂), ammonia (NH₃), nitrogen trioxide(NO₃) or nitrous oxide (N₂O), and an oxygen-containing gas, such asoxygen (O₂) or N₂O. For example, the oxygen-rich first layer can bedeposited over the first deuterated layer by placing the substrate in adeposition chamber and introducing a process gas including N₂O, NH₃ andDCS, while maintaining the chamber at a pressure of from about 5milliTorr (mT) to about 500 mT, and maintaining the substrate at atemperature of from about 700° C. to about 850° C. and in certainembodiments at least about 760° C., for a period of from about 2.5minutes to about 20 minutes. In particular, the process gas can includea first gas mixture of N₂O and NH; mixed in a ratio of from about 8:1 toabout 1:8 and a second gas mixture of DCS and NH₃ mixed in a ratio offrom about 1:7 to about 7:1, and can be introduced at a flow rate offrom about 5 to about 200 standard cubic centimeters per minute (sccm).It has been found that an oxynitride layer produced or deposited underthese condition yields a silicon-rich, oxygen-rich, oxygen-rich firstlayer.

Alternatively, gases in which hydrogen has been replaced by deuteriumcan be used, including, for example, the substitution ofdeuterated-ammonia (ND₃) for NH₃. The substitution of deuterium forhydrogen advantageously passivates Si dangling bonds at thesilicon-oxide interface, thereby increasing an NBTI (Negative BiasTemperature Instability) lifetime of the devices.

An anti-tunneling layer is then formed or deposited on a surface of theoxygen-rich first layer. The anti-tunneling layer can be formed ordeposited by any suitable means, including a plasma oxidation process,In-Situ Steam Generation (ISSG) or a radical oxidation process. In oneembodiment, the radical oxidation process involves flowing hydrogen (H₂)and oxygen (O₂) gas into a batch-processing tool or furnace to effectgrowth of the anti-tunneling layer by oxidation consumption of a portionof the oxygen-rich first layer.

The oxygen-lean second layer of the multi-layer charge-trapping regionis then formed on a surface of the anti-tunneling layer. The oxygen-leansecond layer can be deposited over the anti-tunneling layer in a CVDprocess using a process gas including N₂O, NH₃ and DCS, at a chamberpressure of from about 5 mT to about 500 mT, and at a substratetemperature of from about 700° C. to about 850° C. and in certainembodiments at least about 760° C., for a period of from about 2.5minutes to about 20 minutes. In particular, the process gas can includea first gas mixture of N₂O and NH₃ mixed in a ratio of from about 8:1 toabout 1:8 and a second gas mixture of DCS and NH₃ mixed in a ratio offrom about 1:7 to about 7:1, and can be introduced at a flow rate offrom about 5 to about 20 sccm. It has been found that an oxynitridelayer produced or deposited under these condition yields a silicon-rich,nitrogen-rich, and oxygen-lean second layer.

In some embodiments, the oxygen-lean second layer can be deposited overthe anti-tunneling layer in a CVD process using a process gas includingBTBAS and ammonia (NH₃) mixed at a ratio of from about 7:1 to about 1:7to further include a concentration of carbon selected to increase thenumber of traps therein. The selected concentration of carbon in thesecond oxynitride layer can include a carbon concentration of from about5% to about 15%.

Next, in operation 1206 a blocking layer is formed on the multi-layercharge trapping layer or the split multi-layer charge trapping layer.The blocking layer can be formed by any suitable means including, forexample, thermal oxidation or deposition with CVD techniques. In apreferred embodiment, the blocking layer is formed with ahigh-temperature CVD process. Generally, the deposition process involvesproviding a silicon source, such as SiH₄, SiH₂Cl, or SiCl₄ and anoxygen-containing gas, such as O₂ or N₂O in a deposition chamber at apressure of from about 50 mT to about 1000 mT, for a period of fromabout 10 minutes to about 120 minutes while maintaining the substrate ata temperature of from about 650° C. to about 850° C. Preferably, theblocking layer is deposited sequentially in the same processing toolemployed to form the multi-layer charge trapping layer. More preferably,the blocking layer is formed in the same processing tool as both themulti-layer charge trapping layer and the tunneling layer withoutremoving the substrate between operations.

In the embodiment depicted in FIG. 12, the blocking layer deposited atoperation 1206 is reoxidized at operation 1208 to densify the blockinglayer oxide. As discussed elsewhere herein, operation 1208 may furtheroxidize or reoxidize a portion of the second region 1116B of themulti-layer charge trapping layer 1116 to achieve a graded band gap,such as depicted in FIG. 8A. Generally, the reoxidation may be performedin the presence of an oxidizing gas such as, oxygen (O₂), nitrous oxide(N₂O), nitric oxide (NO), ozone (O₃), and steam (H₂O). In oneembodiment, the reoxidation process may is performed at a highertemperature than the temperature at which the blocking layer isdeposited. Reoxidation after the deposition of the blocking oxideenables a more controlled diffusion of oxidizer to controllably oxidizeor reoxidize a portion of the second region 1116B. In a particularlyadvantageous embodiment, a dilute wet oxidation is employed. The dilutewet oxidation is distinct from a wet oxidation in that the H₂:O₂ ratiois between 1 and 1.3. In one specific embodiment, a dilute oxidationwith an H₂:O₂ ratio of approximately 1.2 is performed at a temperatureof between 800° C. and 900° C.

In a further embodiment, the duration of the dilute oxidation may besufficient to grow between 5.0 nm and 12.5 nm of silicon dioxide on asilicon substrate. In one such embodiment, the duration is sufficient tofor an approximately 10 nm to 1.1 nm silicon dioxide layer on a siliconsubstrate. Such a dilute oxidation process serves to reoxidize thedeposited blocking layer oxide and may further oxidize or reoxidize aportion of the charge trapping layer to impart a band structure likethat depicted in FIG. 8A or 8B.

In another embodiment, the reoxidation of operation 1208 may furtherserve to form a gate oxide in a non-SONOS-type device region, such asfor a complementary metal oxide silicon (CMOS) field effect transistors(FET), on the same substrate as the SONOS-type device. In anotherembodiment, the reoxidation of operation 1208 may further serve todiffuse deuterium into portions of the multi-layer charge trapping layeror blocking layer of the SONOS-type device.

The method may then be completed with formation of a gate layer, such asthe gate layer 1114 of FIG. 11A, and, in certain embodiments, theformation of a gate cap layer, such as gate cap layer 1125 depicted inFIG. 11A. With the completion of the gate stack fabrication, furtherprocessing may occur as known in the art to conclude fabrication of aSONOS-type memory device.

In another aspect the present disclosure is also directed to multigateor multigate-surface memory devices including multi-layer chargetrapping layer overlying two or more sides of a channel region formed onor above a surface of a substrate, and methods of fabricating the same.Multigate devices include both planar and non-planar devices. A planarmultigate device (not shown) generally includes a double-gate planardevice in which a number of first layers are deposited to form a firstgate below a subsequently formed channel region, and a number of secondlayers are deposited thereover to form a second gate. A non-planarmultigate device generally includes a horizontal or vertical channelregion formed on or above a surface of a substrate and surrounded onthree or more sides by a gate.

FIGS. 13A and 13B illustrates one embodiment of a non-planar multigatememory device including a multi-layer charge trapping layer. Referringto FIG. 13A, the memory device 1300, commonly referred to as a finFET,includes a channel region 1302 formed from a thin film or layer ofsilicon containing material overlying a surface 1304 on a substrate 1306connecting a source region 1308 and a drain region 1310 of the memorydevice. The channel region 1302 is enclosed on three sides by a finwhich forms a gate 1312 of the device. As with the embodiments describedabove, the channel region 1302 can comprise polysilicon orrecrystallized polysilicon to form a monocrystalline channel region.Optionally, where the channel region 1302 includes a monocrystallinesilicon, the channel region can be formed to have <100> surfacecrystalline orientation relative to a long axis of the channel region.

The thickness of the gate 1312 (measured in the direction from sourceregion to drain region) determines the effective channel length of thememory device.

In accordance with the present disclosure, the non-planar multigatememory device 1300 of FIG. 13A can include a multi-layer charge trappinglayer, a nitridized oxide tunneling layer, and a densified blockinglayer. FIG. 13B is a cross-sectional view of a portion of the non-planarmemory device of FIG. 13A including a portion of the substrate 1306,channel region 1302 and the gate 1312 illustrating a multi-layer chargetrapping layer 1314 a nitridized oxide tunneling layer 1316, and adensified blocking layer 1318. The gate 1312 further includes a metalgate layer 1320 overlying the blocking layer to form a control gate ofthe memory device 1300. In some embodiments a doped polysilicon may bedeposited instead of metal to provide a polysilicon gate layer. Thechannel region 1302 and gate 1312 can be formed directly on substrate1306 or on an insulating or dielectric layer 1322, such as a buriedoxide layer, formed on or over the substrate.

Referring to FIG. 13B, the tunneling layer 1316 in certain embodiments,such as that shown, is a nitridized oxide tunneling layer 1316 andincludes a first region 1316A proximate to the channel region 1302having a nitrogen concentration less than about 5×10²¹ nitrogenatoms/cm³, and a second region 1316B proximate to the multi-layer chargetrapping layer 1314 having a nitrogen concentration at least 5×10²¹nitrogen atoms/cm³. In one embodiment, similar to that disclosed in FIG.11B, the first and second regions of the nitridized oxide tunnelinglayer 1316 each comprise no more than approximately 25% of the tunnelinglayer thickness.

The multi-layer charge trapping layer 1314 includes at least oneoxygen-rich first layer 1314A including nitride closer to the tunnelinglayer 1316, and an oxygen-lean second layer 1314B overlying theoxygen-rich first layer. Generally, the oxygen-lean second layer 1314Bincludes a silicon-rich, oxygen-lean nitride layer and includes amajority of a charge traps distributed in the multi-layercharge-trapping layer 1314, while the oxygen-rich first layer 1314Aincludes an oxygen-rich nitride or silicon oxynitride, and isoxygen-rich relative to the oxygen-lean second layer to reduce thenumber of charge traps therein. By oxygen-rich it is meant wherein aconcentration of oxygen in the oxygen-rich first layer 1314A is fromabout 15 to about 40%, whereas a concentration of oxygen in theoxygen-lean second layer 1314B is less than about 5%.

In some embodiments, such as that shown in FIG. 13B, the multi-layercharge trapping layer 1314 further includes at least one thin,intermediate or anti-tunneling layer 1314C including a dielectric, suchas an oxide, separating the oxygen-lean second layer 1314B from theoxygen-rich first layer 1314A. As noted above, the anti-tunneling layer1314C substantially reduces the probability of electron charge thataccumulates at the boundaries of the oxygen-lean second layer 1314Bduring programming from tunneling into the oxygen-rich first layer1314A.

As with the embodiments described above, either or both of theoxygen-rich first layer 1314A and the oxygen-lean second layer 1314B caninclude silicon nitride or silicon oxynitride, and can be formed, forexample, by a CVD process including N₂O/NH₃ and DCS/NH₃ gas mixtures inratios and at flow rates tailored to provide a silicon-rich andoxygen-rich oxynitride layer. The oxygen-lean second layer of themulti-layer charge storing structure is then formed on the middle oxidelayer. The oxygen-lean second layer 1314B has a stoichiometriccomposition of oxygen, nitrogen and/or silicon different from that ofthe bottom oxygen-rich first layer 1314A, and may also be formed ordeposited by a CVD process using a process gas including N₂O/NH andDCS/NH₃ gas mixtures in ratios and at flow rates tailored to provide asilicon-rich, oxygen-lean top nitride layer.

In those embodiments including an intermediate or anti-tunneling layer1314C including oxide, the anti-tunneling layer can be formed byoxidation of the oxygen-rich first layer 1314A, to a chosen depth usingradical oxidation. Radical oxidation may be performed, for example, at atemperature of 1000-1100° C. using a single wafer tool, or 800-900° C.using a batch reactor tool. A mixture of H₂ and O₂ gasses may beemployed at a pressure of 300-500 Tor for a batch process, or 10-15 Torusing a single vapor tool, for a time of 1-2 minutes using a singlewafer tool, or 30 min-1 hour using a batch process.

A suitable thickness for the oxygen-rich first layer 1314A may be fromabout 30 Å to about 130 Å (with some variance permitted, for example ±10Å), of which about 5-20 Å may be consumed by radical oxidation to formthe anti-tunneling layer 1314C. A suitable thickness for the oxygen-leansecond layer 1314B may be at least 30 Å. In certain embodiments, theoxygen-lean second layer 1314B may be formed up to 130 Å thick, of which30-70 Å may be consumed by radical oxidation to form the blocking layer1318. A ratio of thicknesses between the oxygen-rich first layer 1314Aand the oxygen-lean second layer 1314B is approximately 1:1 in someembodiments, although other ratios are also possible.

The blocking layer 1318 comprises a high temperature oxide (HTO) whichis relatively denser than as-deposited. A densified HTO has a lowerfraction of terminal hydrogen or hydroxyl bonds. For example, removal ofthe hydrogen or water from an HTO has the effect of increasing the filmdensity and improving the quality of the HTO. The higher quality oxideenables the layer to be scaled in thickness. In one embodiment, thehydrogen concentration is greater than 2.5×1020 atoms/cm3 as depositedand is reduced to below 8.0×1019 atoms/cm3 in the densified film. In anexemplary embodiment, the thickness of the blocking layer 1318comprising a densified HTO is between 2.5 nm and 10.0 nm as-depositedand anywhere between 10% and 30% thinner upon densification.

In an alternate embodiment, the blocking layer 1318 is further modifiedto incorporate nitrogen. In one such embodiment, the nitrogen isincorporated in the form of an ONO stack across the thickness of theblocking layer 1318. Such a sandwich structure in place of theconventional pure oxygen blocking layer advantageously reduces the EOTof the entire stack between the channel region 1302 and control gate1320 as well as enable tuning of band offsets to reduce back injectionof carriers. The ONO stack blocking layer 1318 can then be incorporatedwith the nitridized oxide tunneling layer 1316 and split multi-layercharge trapping layer 1314 comprising an oxygen-rich first layer 1314A,an oxygen-lean second layer 1314B and an anti-tunneling layer 1314C.

In another embodiment, shown in FIGS. 14A and 14B, the memory device caninclude a nanowire channel region formed from a thin film ofsemiconducting material overlying a surface on a substrate connecting asource region and a drain region of the memory device. By nanowirechannel region it is meant a conducting channel region formed in a thinstrip of crystalline silicon material, having a maximum cross-sectionaldimension of about 10 nanometers (nm) or less, and more preferably lessthan about 6 nm. Optionally, the channel region can be formed to have<100> surface crystalline orientation relative to a long axis of thechannel region.

Referring to FIG. 14A, the memory device 1400 includes a horizontalnanowire channel region 1402 formed from a thin film or layer ofsemiconducting material on or overlying a surface on a substrate 1406,and connecting a source region 1408 and a drain region 1410 of thememory device. In the embodiment shown, the device has a gate-all-around(GAA) structure in which the nanowire channel region 1402 is enclosed onall sides by a gate 1412 of the device. The thickness of the gate 1412(measured in the direction from source region to drain region)determines the effective channel length of the device. As with theembodiments described above, the nanowire channel region 1402 cancomprise polysilicon or recrystallized polysilicon to form amonocrystalline channel region. Optionally, where the channel region1402 includes a monocrystalline silicon, the channel region can beformed to have <100> surface crystalline orientation relative to a longaxis of the channel region.

In accordance with the present disclosure, the non-planar multigatememory device 1400 of FIG. 14A can include a multi-layer charge trappinglayer, a nitridized oxide tunneling layer, and a densified blockinglayer. FIG. 14B is a cross-sectional view of a portion of the non-planarmemory device of FIG. 14A including a portion of the substrate 1406,nanowire channel region 1402 and the gate 1412. Referring to FIG. 14B,the gate 1412 includes a nitridized oxide tunneling layer 1414, amulti-layer charge trapping layer 1416, and a densified blocking layer1418. The gate 1412 further includes a gate layer 1420 overlying theblocking layer to form a control gate of the memory device 1400. Thegate layer 1420 can comprise a metal or a doped polysilicon.

The tunneling layer 1414 in certain embodiments, such as that shown, isa nitridized oxide tunneling layer 1414 including a first region 1414Aproximate to the channel region 1402 having a nitrogen concentrationless than about 5×10²¹ nitrogen atoms/cm, and a second region 1414Bproximate to the multi-layer charge trapping layer 1416 having anitrogen concentration at least 5×10²¹ nitrogen atoms/cm³. In oneembodiment, similar to that disclosed in FIG. 11B, the first and secondregions of the nitridized oxide tunneling layer 1414 each comprise nomore than approximately 25% of the tunneling layer thickness.

The multi-layer charge trapping layer 1416 includes at least an inner,oxygen-rich first layer 1416A including nitride closer to the tunnelinglayer 1414, and an outer, oxygen-lean second layer 1416B overlying theoxygen-rich first layer. Generally, the oxygen-lean second layer 1416Bincludes a silicon-rich, oxygen-lean nitride layer and includes amajority of a charge traps distributed in the multi-layercharge-trapping layer 1416, while the oxygen-rich first layer 1416Aincludes an oxygen-rich nitride or silicon oxynitride, and isoxygen-rich relative to the oxygen-lean second layer to reduce thenumber of charge traps therein. By oxygen-rich it is meant wherein aconcentration of oxygen in the oxygen-rich first layer 1416A is fromabout 15 to about 40%, whereas a concentration of oxygen in theoxygen-lean second layer 1416B is less than about 5%.

In some embodiments, such as that shown in FIG. 14B, the multi-layercharge trapping layer 1416 further includes at least one thin,intermediate or anti-tunneling layer 1416C including a dielectric, suchas an oxide, separating the oxygen-lean second layer 1416B from theoxygen-rich first layer 1416A. As noted above, the anti-tunneling layer1416C substantially reduces the probability of electron charge thataccumulates at the boundaries of the oxygen-lean second layer 1416Bduring programming from tunneling into the oxygen-rich first layer1416A.

As with the embodiments described above, either or both of theoxygen-rich first layer 1416A and the oxygen-lean second layer 1416B caninclude silicon nitride or silicon oxynitride, and can be formed, forexample, by a CVD process including N₂O/NH₃ and DCS/NH₃ gas mixtures inratios and at flow rates tailored to provide a silicon-rich andoxygen-rich oxynitride layer. The oxygen-lean second layer of themulti-layer charge storing structure is then formed on the middle oxidelayer. The oxygen-lean second layer 1416B has a stoichiometriccomposition of oxygen, nitrogen and/or silicon different from that ofthe bottom oxygen-rich first layer 1416A, and may also be formed ordeposited by a CVD process using a process gas including DCS/NH₃ andN₂O/NH₃ gas mixtures in ratios and at flow rates tailored to provide asilicon-rich, oxygen-lean top nitride layer.

In those embodiments including an intermediate or anti-tunneling layer1416C including oxide, the anti-tunneling layer can be formed byoxidation of the oxygen-rich first layer 1416A, to a chosen depth usingradical oxidation. Radical oxidation may be performed, for example, at atemperature of 1000-1100° C. using a single wafer tool, or 800-900° C.using a batch reactor tool. A mixture of H₂ and O₂ gasses may beemployed at a pressure of 300-500 Tor for a batch process, or 10-15 Torusing a single wafer tool, for a time of 1-2 minutes using a singlewafer tool, or 30 min-1 hour using a batch process.

A suitable thickness for the oxygen-rich first layer 1416A may be fromabout 30 Å to about 130 Å (with some variance permitted, for example ±10Å), of which about 5-20 Å may be consumed by radical oxidation to formthe anti-tunneling layer 1416C. A suitable thickness for the oxygen-leansecond layer 1416B may be at least 30 Å. In certain embodiments, theoxygen-lean second layer 1416B may be formed up to 130 Å thick, of which30-70 Å may be consumed by radical oxidation to form the blocking layer1418. A ratio of thicknesses between the oxygen-rich first layer 1416Aand the oxygen-lean second layer 1416B is approximately 1:1 in someembodiments, although other ratios are also possible.

The blocking layer 1418 comprises a high temperature oxide (HTO) whichrelatively denser than as-deposited. A densified HTO has a lowerfraction of terminal hydrogen or hydroxyl bonds. For example, removal ofthe hydrogen or water from an HTO has the effect of increasing the filmdensity and improving the quality of the HTO. The higher quality oxideenables the layer to be scaled in thickness. In one embodiment, thehydrogen concentration is greater than 2.5×1020 atoms/cm3 as depositedand is reduced to below 8.0×1019 atoms/cm3 in the densified film. In anexemplary embodiment, the thickness of the blocking layer 1418comprising a densified HTO is between 2.5 nm and 10.0 nm as-depositedand anywhere between 10% and 30% thinner upon densification.

In an alternate embodiment, the blocking layer 1418 is further modifiedto incorporate nitrogen. In one such embodiment, the nitrogen isincorporated in the form of an ONO stack across the thickness of theblocking layer 1418. Such a sandwich structure in place of theconventional pure oxygen blocking layer advantageously reduces the EOTof the entire stack between the channel region 1402 and gate layer 1420as well as enable tuning of band offsets to reduce back injection ofcarriers. The ONO stack blocking layer 1418 can then be incorporatedwith the nitridized oxide tunneling layer 1414 and split multi-layercharge trapping layer 1416 comprising an oxygen-rich first layer 1416A,an oxygen-lean second layer 1416B and an anti-tunneling layer 1416C.

FIG. 14C illustrates a cross-sectional view of a vertical string ofnon-planar multigate devices 1400 of FIG. 14A arranged in a Bit-CostScalable or BiCS architecture 1426. The architecture 1426 consists of avertical string or stack of non-planar multigate devices 1400, whereeach device or cell includes a channel region 1402 overlying thesubstrate 1406, and connecting a source region and a drain region (notshown in this figure) of the memory device, and having a gate-all-around(GAA) structure in which the nanowire channel region 1402 is enclosed onall sides by a gate 1412. The BiCS architecture reduces number ofcritical lithography steps compared to a simple stacking of layers,leading to a reduced cost per memory bit.

In another embodiment, the memory device is or includes a non-planardevice comprising a vertical nanowire channel region formed in or from asemiconducting material projecting above or from a number of conducting,semiconducting layers on a substrate. In one version of this embodiment,shown in cut-away in FIG. 15A, the memory device 1500 comprises avertical nanowire channel region 1502 formed in a cylinder ofsemiconducting material connecting a source region 1504 and drain region1506 of the device. The channel region 1502 is surrounded by a tunnelinglayer 1508, a multi-layer charge trapping layer 1510, a blocking layer1512 and a gate layer 1514 overlying the blocking layer to form acontrol gate of the memory device 1500. The channel region 1502 caninclude an annular region in an outer layer of a substantially solidcylinder of semiconducting material, or can include an annular layerformed over a cylinder of dielectric filler material. As with thehorizontal nanowires described above, the channel region 1502 cancomprise polysilicon or recrystallized polysilicon to form amonocrystalline channel region. Optionally, where the channel region1502 includes a monocrystalline silicon, the channel region can beformed to have <100> surface crystalline orientation relative to a longaxis of the channel region.

In some embodiments, such as that shown in FIG. 15B, the tunneling layer1508, is a nitridized oxide tunneling layer including a first region1508A proximate to the channel region 1502 having a nitrogenconcentration less than about 5×10²¹ nitrogen atoms/cm³, and a secondregion 1508B proximate to the multi-layer charge trapping layer 1510having a nitrogen concentration at least 5×10²¹ nitrogen atoms/cm³. Inone embodiment, similar to that disclosed in FIG. 11B, the first andsecond regions of the nitridized oxide tunneling layer 1508 eachcomprise no more than approximately 25% of the tunneling layerthickness.

The multi-layer charge trapping layer 1510 is a split the multi-layercharge trapping layer further including at least an inner, oxygen-richfirst layer 1510A including nitride closer to the tunneling layer 1508,and an outer, oxygen-lean second layer 1510B overlying the oxygen-richfirst layer. Generally, the oxygen-lean second layer 1510B includes asilicon-rich, oxygen-lean nitride layer and includes a majority of acharge traps distributed in the multi-layer charge-trapping layer 1510,while the oxygen-rich first layer 1510A includes an oxygen-rich nitrideor silicon oxynitride, and is oxygen-rich relative to the oxygen-leansecond layer to reduce the number of charge traps therein. Byoxygen-rich it is meant wherein a concentration of oxygen in theoxygen-rich first layer 1510A is from about 15 to about 40%, whereas aconcentration of oxygen in the oxygen-lean second layer 1510B is lessthan about 5%.

In some embodiments, such as that shown in FIG. 15B, the splitmulti-layer charge trapping layer 1510 further includes at least onethin, intermediate or anti-tunneling layer 1510C including a dielectric,such as an oxide, separating the oxygen-lean second layer 1510B from theoxygen-rich first layer 1510A. As noted above, the anti-tunneling layer1510C substantially reduces the probability of electron charge thataccumulates at the boundaries of the oxygen-lean second layer 1510Bduring programming from tunneling into the oxygen-rich first layer1510A.

As with the embodiments described above, either or both of theoxygen-rich first layer 1510A and the oxygen-lean second layer 1510B caninclude silicon nitride or silicon oxynitride, and can be formed, forexample, by a CVD process including N₂O/NH₃ and DCS/NH₃ gas mixtures inratios and at flow rates tailored to provide a silicon-rich andoxygen-rich oxynitride layer. The oxygen-lean second layer of themulti-layer charge storing structure is then formed on the middle oxidelayer. The oxygen-lean second layer 1510B has a stoichiometriccomposition of oxygen, nitrogen and/or silicon different from that ofthe oxygen-rich first layer 1510A, and may also be formed or depositedby a CVD process using a process gas including DCS/NH₃ and N₂O/NH₃ gasmixtures in ratios and at flow rates tailored to provide a silicon-rich,oxygen-lean top nitride layer.

In those embodiments including an intermediate or anti-tunneling layer1510C including oxide, the anti-tunneling layer can be formed byoxidation of the oxygen-rich first layer 1510A, to a chosen depth usingradical oxidation. Radical oxidation may be performed, for example, at atemperature of 1000-1100° C. using a single wafer tool, or 800-900° C.using a batch reactor tool. A mixture of H₂ and O₂ gasses may beemployed at a pressure of 300-500 Tor for a batch process, or 10-15 Torusing a single vapor tool, for a time of 1-2 minutes using a singlewafer tool, or 30 min-1 hour using a batch process.

A suitable thickness for the oxygen-rich first layer 1510A may be fromabout 30 Å to about 130 Å (with some variance permitted, for example ±10Å), of which about 5-20 Å may be consumed by radical oxidation to formthe anti-tunneling layer 1510C. A suitable thickness for the oxygen-leansecond layer 1510B may be at least 30 Å. In certain embodiments, theoxygen-lean second layer 1510B may be formed up to 130 Å thick, of which30-70 Å may be consumed by radical oxidation to form the blocking layer1512. A ratio of thicknesses between the oxygen-rich first layer 1510Aand the oxygen-lean second layer 1510B is approximately 1:1 in someembodiments, although other ratios are also possible.

The blocking layer 1512 comprises a high temperature oxide (HTO) whichis relatively denser than as-deposited. A densified HTO has a lowerfraction of terminal hydrogen or hydroxyl bonds. For example, removal ofthe hydrogen or water from an HTO has the effect of increasing the filmdensity and improving the quality of the HTO. The higher quality oxideenables the layer to be scaled in thickness. In one embodiment, thehydrogen concentration is greater than 2.5×1020 atoms/cm3 as depositedand is reduced to below 8.0×1019 atoms/cm3 in the densified film. In anexemplary embodiment, the thickness of the blocking layer 1512comprising a densified HTO oxide is between 2.5 nm and 10.0 nmas-deposited and anywhere between 10% and 30% thinner upondensification.

In an alternate embodiment, the blocking layer 1512 is further modifiedto incorporate nitrogen. In one such embodiment, the nitrogen isincorporated in the form of an ONO stack across the thickness of theblocking layer 1512. Such a sandwich structure in place of theconventional pure oxygen blocking layer advantageously reduces the EOTof the entire stack between the channel region 1502 and gate layer 1514as well as enable tuning of band offsets to reduce back injection ofcarriers. The ONO stack blocking layer 1512 can then be incorporatedwith the nitridized oxide tunneling layer 1508 and split multi-layercharge trapping layer 1510 comprising an oxygen-rich first layer 1510A,an oxygen-lean second layer 1510B and an anti-tunneling layer 1510C.

The memory device 1500 of FIG. 15A can be made using either a gate firstor a gate last scheme. FIGS. 16A-F illustrate a gate first scheme forfabricating the non-planar multigate device of FIG. 15A. FIGS. 17A-Fillustrate a gate last scheme for fabricating the non-planar multigatedevice of FIG. 15A.

Referring to FIG. 16A, in a gate first scheme a first or lowerdielectric layer 1602, is formed over a first, doped diffusion region1604, such as a source region or a drain region, in a substrate 1606. Agate layer 1608 is deposited over the first dielectric layer 1602 toform a control gate of the device, and a second or upper dielectriclayer 1610 formed thereover. As with embodiments described above, thefirst and second dielectric layers 1602, 1610, can be deposited by CVD,radical oxidation or be formed by oxidation of a portion of theunderlying layer or substrate. The gate layer 1608 can comprise a metaldeposited or a doped polysilicon deposited by CVD. Generally thethickness of the gate layer 1608 is from about 40-110 Å, and the firstand second dielectric layers 1602, 1610, from about 20-80 Å.

Referring to FIG. 16B, a first opening 1612 is etched through the seconddielectric layer 1610, the gate layer 1608, and the first dielectriclayer 1602 to the diffusion region 1604 in the substrate 1606. Next,layers of a blocking layer 1614, multi-layer charge trapping layer 1616,and tunneling layer 1618 are sequentially deposited in the opening andthe surface of the upper dielectric layer 1610 planarize to yield theintermediate structure shown in FIG. 16C.

As in the embodiments described above the blocking layer 1614 can be adensified blocking layer, comprising a densified HTO which is relativelydenser than as-deposited, and has a lower fraction of terminal hydrogenor hydroxyl bonds.

Although not shown, it will be understood that as in the embodimentsdescribed above the multi-layer charge trapping layer 1616 can include asplit multi-layer charge trapping layer comprising an outer, oxygen-leansecond layer closer to or deposited on the densified blocking layer1614, and an inner, oxygen-rich first layer deposited or formed on theoxygen-lean second layer. Generally, the oxygen-lean second layercomprises a silicon-rich, oxygen-lean nitride layer and comprises amajority of a charge traps distributed in multiple charge-trappinglayers, while the oxygen-rich first layer comprises an oxygen-richnitride or silicon oxynitride, and is oxygen-rich relative to the topcharge-trapping layer to reduce the number of charge traps therein. Insome embodiments, the multi-layer charge trapping layer 1616 is a splitmulti-layer charge trapping layer further including at least one thin,intermediate or anti-tunneling layer comprising a dielectric, such as anoxide, separating the outer, oxygen-lean second layer closer from theinner, oxygen-rich first layer.

It will further be understood that the tunneling layer 1618 is anitridized oxide tunneling layer, and can include a first region havinga nitrogen concentration less than about 5×10²¹ nitrogen atoms/cm³overlying a second region proximate to the multi-layer charge trappinglayer 1616 having a nitrogen concentration at least 5×10²¹ nitrogenatoms/cm³.

Next, referring to FIG. 16D, a second or channel opening 1620 isanisotropically etched through tunneling layer 1618, multi-layer chargetrapping layer 1616, and blocking layer 1614 to expose a portion of thediffusion region 1604 in the substrate 1606. Referring to FIG. 16E, asemiconducting material 1622 is deposited in the channel opening to forma vertical channel region 1624 therein. The vertical channel region 1624can include an annular region in an outer layer of a substantially solidcylinder of semiconducting material, or, as shown in FIG. 16E, caninclude a separate, layer of semiconducting material 1622 surrounding acylinder of filler material 1626.

Referring to FIG. 16F, the surface of the upper dielectric layer 1610 isplanarized and a layer of semiconducting material 1628 including asecond, doped diffusion region 1630, such as a source region or a drainregion, formed therein deposited over the upper dielectric layer to formthe device shown.

Referring to FIG. 17A, in a gate last scheme a dielectric layer 1702,such as an oxide, is formed over a sacrificial layer 1704 on a surfaceon a substrate 1706, an opening etched through the dielectric andsacrificial layers and a vertical channel region 1708 formed therein. Aswith embodiments described above, the vertical channel region 1708 caninclude an annular region in an outer layer of a substantially solidcylinder of semiconducting material 1710, such as polycrystalline ormonocrystalline silicon, or can include a separate, layer ofsemiconducting material surrounding a cylinder of dielectric fillermaterial (not shown). The dielectric layer 1702 can comprise anysuitable dielectric material, such as a silicon oxide, capable ofelectrically isolating the subsequently formed gate layer of the memorydevice 1500 from an overlying electrically active layer or anothermemory device. The sacrificial layer 1704 can comprise any suitablematerial that can be etched or removed with high selectivity relative tothe material of the dielectric layer 1702, substrate 1706 and verticalchannel region 1708.

Referring to FIG. 17B, a second opening 1712 is etched through thedielectric and sacrificial layers 1702, 1704, to the substrate 1706, andthe sacrificial layer 1704 at least partially etched or removed. Thesacrificial layer 1704 can comprise any suitable material that can beetched or removed with high selectivity relative to the material of thedielectric layer 1702, substrate 1706 and vertical channel region 1708.In one embodiment the sacrificial layer 1704 comprises that can beremoved by Buffered Oxide Etch (BOE etch).

Referring to FIGS. 17C and 17D, layers of a tunneling layer 1714A-Bcomprising a nitridized oxide, a multi-layer charge trapping layer1716A-C, and a blocking layer 1718 are sequentially deposited in theopening and the surface of the dielectric layer 1702 planarize to yieldthe intermediate structure shown in FIG. 17C. As in the embodimentsdescribed above the blocking layer 1718 can be a densified blockinglayer, comprising a densified HTO which is relatively denser thanas-deposited, and has a lower fraction of terminal hydrogen or hydroxylbonds

In some embodiments, such as that shown in FIG. 17D, the nitridizedoxide tunneling layer including a first region 1714A proximate to thesemiconducting material 1710 having a nitrogen concentration less thanabout 5×10²¹ nitrogen atoms/cm³ and a second region 1714B proximate tothe multi-layer charge trapping layer 1716A-C having a nitrogenconcentration at least 5×10²¹ nitrogen atoms/cm.

The multi-layer charge trapping layer 1716A-C is a split multi-layercharge trapping layer including at least an inner oxygen-rich firstlayer 1716A closest to the nitridized oxide tunneling layer 1714, and anouter, oxygen-lean second layer 1716B. Optionally, the first and secondcharge trapping layers can be separated by an intermediate oxide oranti-tunneling layer 1716C.

Next, a gate layer 1722 is deposited into the second opening 1712 andthe surface of the upper dielectric layer 1702 planarized to yield theintermediate structure illustrated in FIG. 17E As with embodimentsdescribed above, the gate layer 1722 can comprise a metal deposited or adoped polysilicon. Finally, an opening 1724 is etched through the gatelayer 1722 to form control gate of separate memory devices 1726A and1726B.

Thus, a method for fabricating a nonvolatile charge trap memory devicehas been disclosed. In accordance with an embodiment of the presentinvention, a substrate is subjected to a first radical oxidation processto form a first dielectric layer in a first process chamber of a clustertool. A charge-trapping layer may then be deposited above the firstdielectric layer in a second process chamber of the cluster tool. In oneembodiment, the charge-trapping layer is then subjected to a secondradical oxidation process to form a second dielectric layer above thecharge-trapping layer by oxidizing a portion of the charge-trappinglayer in the first process chamber of the cluster tool. By forming alllayers of an oxide-nitride-oxide (ONO) stack in a cluster tool,interface damage may be reduced between the respective layers. Thus, inaccordance with an embodiment of the present invention, an ONO stack isfabricated in a single pass in a cluster tool in order to preserve apristine interface between the layers in the ONO stack. In a specificembodiment, the cluster tool is a single-wafer cluster tool.

What is claimed is:
 1. A method comprising: forming a polysiliconchannel region; forming a tunneling layer over the polysilicon channelregion; forming a multi-layer charge trapping layer on the tunnelinglayer, wherein the multi-layer charge trapping layer comprises anoxygen-rich layer and an oxygen-lean layer; and forming a blocking layeron the multi-layer charge trapping layer.